Intra-block copy decoding using dynamic re-mapping of on-chip memory
A device includes a decoder configured to identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address in a virtual address space associated with a read operation of the IBC decoding process. The target virtual address is generated according to an addressing scheme of an on-chip memory used by the IBC decoding process. The decoder is configured to identify, based on the target virtual address, an on-chip memory start address of a portion of the on-chip memory. The on-chip memory is configured to store reconstructed blocks of the video data. The decoder is also configured to perform the read operation to read a block of pixel data from the on-chip memory using the on-chip memory start address.
1. A device comprising:
a decoder configured to:
identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address in a virtual address space associated with a read operation of the IBC decoding process, the target virtual address generated according to an addressing scheme of an on-chip memory used by the IBC decoding process;
identify, based on the target virtual address, an on-chip memory start address of a portion of the on-chip memory, the on-chip memory configured to store reconstructed blocks of the video data; and
perform the read operation to read a block of pixel data from the on-chip memory using the on-chip memory start address.
2. The device of claim 1 , wherein the decoder is configured to, prior to performing the read operation:
perform a write operation to write the block of pixel data to the portion of the on-chip memory; and
store the target virtual address into a data structure that associates virtual start addresses with portions of the on-chip memory.
3. The device of claim 2 , wherein the decoder is configured to locate the on-chip memory start address in the data structure to identify the on-chip memory start address corresponding to the target virtual address associated with the read operation.
4. The device of claim 1 , wherein the decoder is configured to identify the on-chip memory start address based on at least one of a current buffer index and a start address array associated with data in the on-chip memory.
5. The device of claim 1 , wherein a second stored virtual start address is associated with another portion of the on-chip memory, and wherein the decoder is configured to add a block size to the second stored virtual start address to determine an intermediate value and apply a modulo to the intermediate value to determine the target virtual address for the block of pixel data, the modulo associated with a row size of the virtual address space.
6. The device of claim 1 , wherein the on-chip memory is configured as a circular buffer to store pixel data of a current block of the video data and reconstructed blocks of the video data that are within a permitted motion vector range for IBC coding, and wherein the circular buffer overwrites pixel data of reconstructed blocks that are no longer within the permitted motion vector range of the current block.
7. The device of claim 1 , wherein the on-chip memory and the decoder are integrated into a single substrate.
8. The device of claim 1 , wherein the virtual address space has a first size that is at least two times larger than a second size of the on-chip memory.
9. The device of claim 1 , wherein the on-chip memory comprises a static random access memory (SRAM) IBC circular buffer.
10. The device of claim 1 , wherein the addressing scheme corresponds to a Versatile Video Coding (VVC) addressing scheme for IBC decoding.
11. The device of claim 1 , wherein the decoder is further configured to access the on-chip memory during performance of a loop filtering operation associated with the IBC decoding process.
12. The device of claim 1 , further comprising a modem coupled to the decoder, the modem configured to receive the video data from a second device.
13. The device of claim 1 , wherein the decoder and the on-chip memory are integrated in at least one of a mobile phone, a tablet computer device, a wearable electronic device, a camera device, a virtual reality headset, a mixed reality headset, or an augmented reality headset.
14. The device of claim 1 , wherein the decoder and the on-chip memory are integrated in a vehicle, the vehicle further including a display device configured to display video data output by the decoder.
15. A method of decoding video data, the method comprising:
identifying, at one or more processors during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of the video data, a target virtual address in a virtual address space associated with a read operation of the IBC decoding process, the target virtual address generated according to an addressing scheme of an on-chip memory used by the IBC decoding process;
identifying, at the one or more processors and based on the target virtual address, an on-chip memory start address of a portion of the on-chip memory, the on-chip memory configured to store reconstructed blocks of the video data; and
performing the read operation to read a block of pixel data from the on-chip memory using the on-chip memory start address.
16. The method of claim 15 , wherein the virtual address space has a first size that is greater than a second size of the on-chip memory.
17. The method of claim 15 , wherein the on-chip memory start address is associated with a previously used virtual address in the virtual address space prior to the on-chip memory start address being associated with the target virtual address.
18. The method of claim 15 , further comprising adding a block size to a second stored virtual start address to determine an intermediate value, the second stored virtual start address associated with another portion of the on-chip memory, wherein a modulo is applied to the intermediate value to determine the target virtual address for the block of pixel data, and wherein the modulo is associated with a row size of the virtual address space.
19. The method of claim 15 , wherein the identifying the on-chip memory start address includes locating the on-chip memory start address for the block of pixel data in a data structure that associates virtual start addresses with portions of the on-chip memory.
20. The method of claim 15 , wherein the on-chip memory comprises a static random access memory (SRAM) IBC circular buffer.
21. The method of claim 15 , wherein the addressing scheme corresponds to a Versatile Video Coding (VVC) addressing scheme for IBC decoding.
22. A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to:
identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address in a virtual address space associated with a read operation of the IBC decoding process, the target virtual address generated according to an addressing scheme of an on-chip memory used by the IBC decoding process;
identify, based on the target virtual address, an on-chip memory start address of a portion of the on-chip memory, the on-chip memory configured to store reconstructed blocks of the video data; and
perform the read operation to read a block of pixel data from the on-chip memory using the on-chip memory start address.
23. The non-transitory computer-readable medium of claim 22 , wherein the instructions, when executed by the one or more processors, further cause the one or more processors to identify the on-chip memory start address based on at least one of a current buffer index and a start address array associated with data in the on-chip memory.
24. The non-transitory computer-readable medium of claim 22 , wherein the instructions, when executed by the one or more processors, further cause the one or more processors to add a block size to a second stored virtual start address to determine an intermediate value, the second stored virtual start address associated with another portion of the on-chip memory, wherein a modulo is applied to the intermediate value to determine the target virtual address for the block of pixel data, and wherein the modulo is associated with a row size of the virtual address space.
25. The non-transitory computer-readable medium of claim 22 , wherein the on-chip memory is configured as a circular buffer to store pixel data of a current block of the video data and reconstructed blocks of the video data that are within a permitted motion vector range for IBC coding, and wherein the circular buffer overwrites pixel data of reconstructed blocks that are no longer within the permitted motion vector range of the current block.
26. The non-transitory computer-readable medium of claim 22 , wherein the virtual address space has a first size that is at least two times larger than a second size of the on-chip memory.
27. The non-transitory computer-readable medium of claim 22 , wherein the on-chip memory comprises a static random access memory (SRAM) IBC circular buffer.
28. The non-transitory computer-readable medium of claim 22 , wherein the addressing scheme corresponds to a Versatile Video Coding (VVC) addressing scheme for IBC decoding.
29. The non-transitory computer-readable medium of claim 22 , wherein the instructions, when executed by the one or more processors, further cause the one or more processors to access the on-chip memory during performance of a loop filtering operation associated with the IBC decoding process.
30. The non-transitory computer-readable medium of claim 22 , wherein the instructions, when executed by the one or more processors, further cause the one or more processors to receive the video data via a modem from a second device.