IP Library › Granted Patent US 7,400,683
Granted Patent B2
US 7,400,683 · App. 10/716,222 · Granted Jul 15, 2008

Device with virtual tilized image memory

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 7,400,683
App. No.
10/716,222
Granted
Jul 15, 2008
Kind
B2
Abstract

A device generally having a memory manager and a direct memory access unit. The memory manager may be configured to (i) map a first picture from a video signal among a plurality of picture segments and (ii) generate a list associating each of the picture segments to a plurality of physical pages in a memory. The direct memory access unit may be configured to store the first picture among the physical pages according to the list and the mapping.

Claims (40)

1. A device comprising:

a decode processor configured to (i) divide a first picture from a video signal into a plurality of picture segments, (ii) divide each one of said picture segments into a plurality of tiles and (iii) generate a list associating each one of said tiles to a corresponding one page of a plurality of pages in a corresponding one bank of a plurality of banks in a first memory such that each one of said picture segments has (a) at least a first one of said tiles associated with a first of said banks and (b) at least a second one of said tiles associated with a second of said banks;

a direct memory access unit configured to store said first picture in said first memory according to said list; and

a memory manager configured to (i) generate a map allocating space in said first memory to store said first picture and (ii) transfer an identification value identifying said map to said decode processor, wherein (a) said decode processor is further configured to transfer said identification value to said direct memory access unit and (b) said direct memory access unit is further configured to use said identification value to locate said map.

2. The device according to claim 1 , further comprising a second memory configured to (i) store said list and (ii) transfer said list to said direct memory access unit.

3. The device according to claim 1 , wherein said memory manager stores said map in a second memory.

4. The device according to claim 3 , wherein said direct memory access unit uses said identification value to locate said map in said second memory.

5. The device according to claim 1 , wherein each one of said picture segments comprises four of said tiles spatially arranged to share a common corner.

6. The device according to claim 1 , wherein each of said picture segments is mapped to at least four of said banks in said first memory.

7. The device according to claim 1 , wherein said picture segments of said first picture are stored in a plurality of physically non-contiguous address ranges in said first memory.

8. The device according to claim 1 , wherein each of said picture segments comprises one group of a plurality of luminance samples and a plurality of chrominance samples from said first picture.

9. The device according to claim 1 , wherein said tiles comprise a plurality of spatially square regions.

10. The device according to claim 1 , wherein said picture segments comprise a plurality of spatially square regions.

11. A method of storing a video signal, comprising the steps of:

(A) dividing a first picture from said video signal into a plurality of picture segments;

(B) dividing each one of said picture segments into a plurality of tiles;

(C) generating a list associating each one of said tiles to a corresponding one page of a plurality of pages in a corresponding one bank of a plurality of banks in a memory such that each one of said picture segments has (a) at least a first one of said tiles associated with a first of said banks and (b) at least a second one of said tiles associated with a second of said banks;

(D) storing said first picture in said memory according to said list;

(E) generating a map in a memory manager allocating space in said memory to store said first picture;

(F) transferring an identification value identifying said map from said memory manager to a decode processor;

(G) transferring said identification value from said decode processor to a direct memory access unit; and

(H) locating said map with said direct memory access unit using said identification value.

12. The method according to claim 11 , wherein step (D) comprises the sub-step of:

storing said first picture using a plurality of direct memory access operations.

13. The method according to claim 11 , further comprising the step of:

marking a plurality of memory segments in said memory that have been allocated to said first picture as used.

14. The method according to claim 11 , further comprising the step of:

deallocating said memory segments from said first picture to free space in said memory.

15. The method according to claim 14 , further comprising the step of:

marking said memory segments deallocated from said first picture as free.

16. The method according to claim 14 , further comprising the step of:

mapping a second picture from said video signal to said memory segments including at least one of said memory segments deallocated from said first picture.

17. The method according to claim 16 , wherein said first picture has a different size than said second picture.

18. The method according to claim 11 , further comprising the step of:

generating a value identifying which of a plurality of memory segments in said memory are mapped to said first picture.

19. The method according to claim 11 , wherein each one of said picture segments is mapped to all of said banks in said memory.

20. A device comprising:

means for (i) dividing a first picture from a video signal into a plurality of picture segments, (ii) dividing each one of said picture segments into a plurality of tiles and (iii) generating a list associating each one of said tiles to a corresponding one page of a plurality of pages in a corresponding one bank of a plurality of banks in a memory such that each one of said picture segments has (a) at least a first one of said tiles associated with a first of said banks and (b) at least a second one of said tiles associated with a second of said banks;

means for storing said first picture in said memory according to said list; and

means for (i) generating a map allocating space in said memory to store said first picture and (ii) transferring an identification value identifying said map to said means for dividing said first picture, wherein (a) said means for dividing said first picture transfers said identification value to said means for storing and (b) said means for storing uses said identification value to locate said map.

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2003
From: LINZER, ELLIOT N.
To: LSI LOGIC CORPORATION
Reel/Frame 014715/0233 →
Continuity (1)
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