Synchronous rectification circuit
The present application provides a synchronous rectification circuit, which adopts a multiplexer that selectively inputs a first reference signal or a second reference signal to a comparator by coupling the first and second reference signal. A comparing signal is generated to a switch element by comparing a switch input signal. Hereby, the switch element is under control for synchronous rectification.
1. A synchronous rectification circuit, comprising:
a multiplexer, including two input terminals and an output terminal;
a comparator, coupled to said output terminal of said multiplexer; and
a switch, including a control terminal coupled to said comparator;
wherein a first reference signal and a second reference signal are coupled to said two input terminals of said multiplexers; said multiplexer selectively outputs said first reference signal or said second reference signal to said comparator according to a comparison reference signal; and said comparator compares a detection signal of said switch according to said first reference signal or said second reference signal and generates a comparison result signal to said switch, and wherein said comparator compares said first reference signal with said detection signal; when said detection signal is smaller than said first reference signal, said comparison result signal controls said switch to turn on; said comparator compares said second reference signal with said detection signal; and when said detection signal is greater than said second reference signal, said comparison result signal controls said switch to cut off.
2. The synchronous rectification circuit of claim 1 , wherein said detection signal represents an input voltage signal of said switch.
3. The synchronous rectification circuit of claim 1 , wherein said comparison reference signal is said comparison result signal.
4. The synchronous rectification circuit of claim 1 , wherein said comparison reference signal is said comparison result signal after delaying.
5. The synchronous rectification circuit of claim 1 , further comprising:
a driving circuit, coupled to said comparator and said control terminal of said switch for outputting a driving control signal to said switch according to said comparison result signal output by said comparator.
6. The synchronous rectification circuit of claim 1 , wherein when said comparison reference signal is at a first level, said multiplexer transmits said first reference signal to said comparator; when said comparison reference signal is at a second level, said multiplexer transmits said second reference signal to said comparator.
7. The synchronous rectification circuit of claim 1 , wherein said comparator includes a positive input terminal and a negative input terminal; said detection signal is coupled to said negative input terminal; and said output terminal of said multiplexer is coupled to said positive input terminal.
8. A synchronous rectification circuit, comprising:
a multiplexer, including two input terminals and an output terminal;
a comparator, coupled to said output terminal of said multiplexer;
a switch, including a control terminal coupled to said comparator; and
a delay circuit, coupled between said multiplexer and said comparator;
wherein a first reference signal and a second reference signal are coupled to said two input terminals of said multiplexers; said multiplexer selectively outputs said first reference signal or said second reference signal to said comparator according to a comparison reference signal; and said comparator compares a detection signal of said switch according to said first reference signal or said second reference signal and generates a comparison result signal to said switch, and wherein said delay circuit delays said comparison result signal for a predetermined time for forming said comparison reference signal transmitted to said multiplexer.
9. A synchronous rectification circuit, comprising:
a multiplexer, including two input terminals and an output terminal;
a comparator, coupled to said output terminal of said multiplexer; and
a switch, including a control terminal coupled to said comparator;
wherein a first reference signal and a second reference signal are coupled to said two input terminals of said multiplexers; said multiplexer selectively outputs said first reference signal or said second reference signal to said comparator according to a comparison reference signal; and said comparator compares a detection signal of said switch according to said first reference signal or said second reference signal and generates a comparison result signal to said switch; and wherein said comparator includes a positive input terminal and a negative input terminal; said output terminal of said multiplexer is coupled to said positive input terminal; said multiplexer further includes another input terminal and another output terminal; said detection signal is coupled to said another input terminal; and said another output terminal is coupled to said negative input terminal.
10. The synchronous rectification circuit of claim 9 , wherein when said comparison reference signal is at a first level, said multiplexer transmits said first reference signal to said positive input terminal of said comparator and said detection signal to said negative input terminal of said comparator; when said comparison reference signal is at a second level, said multiplexer transmits said detection signal to said positive input terminal of said comparator and said second reference signal to said negative input terminal of said comparator.