IP Library › Granted Patent US 12,237,771
Granted Patent B2
US 12,237,771 · App. 18/489,639 · Granted Feb 25, 2025

Three-level buck converter configurable for two-level buck converter mode operation

Inventors: Sanghwa Jung (Los Gatos, CA); Chunping Song (Palo Alto, CA); Ta-Tung Yen (San Jose, CA); Yue Jing (Santa Clara, CA)
Assignee: QUALCOMM Incorporated
H02M3/1582H02M3/07
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Quick Facts
Patent No.
US 12,237,771
App. No.
18/489,639
Granted
Feb 25, 2025
Kind
B2
Abstract

A three-level buck converter circuit configurable to transition between a three-level buck converter mode and a two-level buck converter mode and methods for regulating power using such a circuit. One example power supply circuit generally includes a three-level buck converter circuit and a control circuit coupled to the three-level buck converter circuit and configured to control operation of the three-level buck converter circuit between a three-level buck converter mode and a two-level buck converter mode. The three-level buck converter circuit generally includes a first switch, a second switch coupled to the first switch via a first node, a third switch coupled to the second switch via a second node, a fourth switch coupled to the third switch via a third node, a first capacitive element coupled between the first node and the third node, and an inductive element coupled between the second node and an output node.

Claims (45)

1. A power supply circuit comprising:

a three-level buck converter circuit comprising a plurality of switches; and

a control circuit coupled to the three-level buck converter circuit and configured to control operation of the plurality of switches to operate between a three-level buck converter mode and a two-level buck converter mode, wherein the control circuit is configured to control the operation of the plurality of switches to exit the two-level buck converter mode based on an output current of the three-level buck converter circuit being higher than a threshold.

2. The power supply circuit of claim 1 , wherein in the two-level buck converter mode, the control circuit is configured to:

control closure of a first pair of switches in the plurality of switches and control opening of a second pair of switches in the plurality of switches, in a first phase of the two-level buck converter mode; and

control opening of the first pair of switches and control closure of the second pair of switches, in a second phase of the two-level buck converter mode.

3. The power supply circuit of claim 2 , wherein in the two-level buck converter mode, the control circuit is configured to control the closure of the first pair of switches with a constant on-time in the first phase of the two-level buck converter mode.

4. The power supply circuit of claim 2 , wherein in the two-level buck converter mode, the control circuit is configured to control the closure of the first pair of switches according to a peak current in the first phase of the two-level buck converter mode.

5. The power supply circuit of claim 1 , wherein in the two-level buck converter mode, the control circuit is configured to:

control closure of a first group of switches in the plurality of switches and control opening of a second group of switches in the plurality of switches, in a first phase of the two-level buck converter mode; and

control opening of the first group of switches and control opening of the second group of switches, in a second phase of the two-level buck converter mode.

6. The power supply circuit of claim 5 , wherein the three-level buck converter circuit further comprises a first capacitive element and a second capacitive element, coupled to the plurality of switches.

7. The power supply circuit of claim 6 , wherein in the two-level buck converter mode:

the second capacitive element is configured to be effectively connected in series with the first capacitive element in the first phase; and

the second capacitive element is configured to be effectively connected in parallel with the first capacitive element in the second phase.

8. The power supply circuit of claim 6 , wherein a capacitance of the second capacitive element is substantially equal to a capacitance of the first capacitive element.

9. The power supply circuit of claim 5 , wherein an on-time interval of the first phase differs from an off-time interval of the second phase.

10. The power supply circuit of claim 5 , wherein the first group of switches comprises a first trio of switches and wherein the second group of switches comprises a second trio of switches, different from the first trio of switches.

11. The power supply circuit of claim 5 , wherein in the two-level buck converter mode, the control circuit is configured to:

control closure of a switch in the first group of switches based on closure of at least two other switches in the first group of switches; and

control closure of a switch in the second group of switches based on closure of at least two other switches in the second group of switches.

12. The power supply circuit of claim 5 , wherein in the three-level buck converter mode, the control circuit is configured to:

control closure of a first switch in the first group of switches based on closure of a second switch in the first group of switches and a first switch in the second group of switches; and

control closure of a second switch in the second group of switches based on closure of a third switch in the first group of switches and a third switch in the second group of switches.

13. A method of regulating power, the method comprising:

operating a three-level buck converter circuit in a two-level buck converter mode, wherein the three-level buck converter circuit comprises a plurality of switches;

determining an output current of the three-level buck converter circuit, while operating in the two-level buck converter mode, is higher than a threshold; and

based on the determination, exiting the two-level buck converter mode and operating the three-level buck converter circuit in a three-level buck converter mode.

14. The method of claim 13 , wherein operating the three-level buck converter circuit in the two-level buck converter mode comprises:

in a first phase of the two-level buck converter mode, closing a first pair of switches in the plurality of switches and opening a second pair of switches in the plurality of switches; and

in a second phase of the two-level buck converter mode, opening the first pair of switches and closing the second pair of switches.

15. The method of claim 14 , wherein closing the first pair of switches comprises closing the first pair of switches with a constant on-time in the first phase of the two-level buck converter mode.

16. The method of claim 14 , wherein closing the first pair of switches comprises closing the first pair of switches according to a peak current in the first phase of the two-level buck converter mode.

17. The method of claim 13 , wherein operating the three-level buck converter circuit in the two-level buck converter mode comprises:

in a first phase of the two-level buck converter mode, closing a first group of switches in the plurality of switches and opening a second group of switches in the plurality of switches; and

in a second phase of the two-level buck converter mode, opening the first group of switches and closing the second group of switches.

18. The method of claim 17 , wherein the three-level buck converter circuit further comprises a first capacitive element and a second capacitive element, coupled to the plurality of switches, and wherein the method further comprises:

effectively connecting the second capacitive element in series with the first capacitive element in the first phase of the two-level buck converter mode; and

effectively connecting the second capacitive element in parallel with the first capacitive element in the second phase of the two-level buck converter mode.

19. The method of claim 17 , wherein operating the three-level buck converter circuit in the two-level buck converter mode comprises:

closing a switch in the first group of switches based on closure of at least two other switches in the first group of switches; and

closing a switch in the second group of switches based on closure of at least two other switches in the second group of switches.

20. The method of claim 17 , wherein operating the three-level buck converter circuit in the three-level buck converter mode comprises:

closing a first switch in the first group of switches based on closure of a second switch in the first group of switches and a first switch in the second group of switches; and

closing a second switch in the second group of switches based on closure of a third switch in the first group of switches and a third switch in the second group of switches.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2023
From: JUNG, SANGHWA; SONG, CHUNPING; YEN, TA-TUNG; JING, YUE
To: QUALCOMM INCORPORATED
Reel/Frame 065469/0071 →
Continuity (2)
Continuation 17363948 · Jun 30, 2021
Related Publication 20240055992A1 · Feb 15, 2024
References Cited (5)
US 10886851B1 · Fletcher · 2021 [cited by applicant]
US 20150311804A1 · Fang · 2015 [cited by examiner]
US 20200161976A1 · Song et al. · 2020 [cited by applicant]
US 20210234463A1 · Fletcher · 2021 [cited by examiner]
US 20230006555A1 · Jung · 2023 [cited by applicant]