Array substrate and display apparatus
An array substrate is provided. The array substrate includes a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements. In a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent. In a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent.
1. An array substrate, comprising:
a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements; and
a plurality of connecting lines connecting the plurality of pixel driving circuits with the plurality of light emitting elements, respectively;
wherein, in a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent; and
in a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent;
wherein an orthographic projection of a respective connecting line of the plurality of connecting lines on a base substrate intersects with an orthographic projection of at least one row of pixel driving circuits other than the respective pixel driving circuit on the base substrate;
wherein the plurality of connecting lines are arranged in an array comprising rows and columns, the array being at least partially present in the first region and at least partially present in the second region.
2. The array substrate of claim 1 , wherein, in the first region, transistors of at least one row of pixel driving circuits are present, and the plurality of light emitting elements are absent; and
in the second region, at least one row of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent.
3. The array substrate of claim 1 , wherein, in a third region, multiple rows of light emitting elements and transistors of multiple rows of pixel driving circuits are present; and
the first region and the second region are on two sides of the third region.
4. The array substrate of claim 1 , wherein included angles between extension directions of the plurality of connecting lines are between 0 degree to 30 degrees.
5. The array substrate of claim 1 , wherein a ratio of a total number of rows of connecting lines to a total number of rows of subpixels configured to emit light is in a range of 0.9 to 1.1, and a ratio of a total number of columns of connecting lines to a total number of columns of subpixels configured to emit light is in a range of 0.9 to 1.1.
6. The array substrate of claim 1 , wherein the plurality of connecting lines extend along a direction from the first region to the second region.
7. The array substrate of claim 1 , wherein the plurality of connecting lines are in a third signal line layer;
wherein the array substrate further comprises:
a second planarization layer on a side of the third signal line layer closer to a base substrate;
a third planarization layer on a side of the third signal line layer away from the base substrate; and
an anode layer on a side of the third planarization layer away from the third signal line layer;
wherein the plurality of pixel driving circuits are on a side of the second planarization layer away from the third signal line layer.
8. The array substrate of claim 1 , wherein an orthographic projection of a respective light emitting layer of a respective light emitting element of the plurality of light emitting elements on a base substrate is non-overlapping with an orthographic projection of a corresponding pixel driving circuit of the plurality of pixel driving circuits on the base substrate, the corresponding pixel driving circuit configured to drive light emission in the respective light emitting element.
9. The array substrate of claim 1 , wherein an orthographic projection of a respective anode of a respective light emitting element of the plurality of light emitting elements on a base substrate is non-overlapping with an orthographic projection of a corresponding pixel driving circuit of the plurality of pixel driving circuits on the base substrate, the corresponding pixel driving circuit configured to drive light emission in the respective light emitting element.
10. The array substrate of claim 1 , wherein orthographic projections of any electrically connected pair of pixel driving circuit and anode on a base substrate are non-overlapping; and
any pair of pixel driving circuit and anode having overlapping orthographic projections on the base substrate are electrically separated.
11. A display apparatus, comprising the array substrate of claim 1 , and one or more integrated circuit connected to the array substrate.
12. An array substrate, comprising:
a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements; and
a plurality of connecting lines connecting the plurality of pixel driving circuits with the plurality of light emitting elements, respectively;
wherein, in a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent; and
in a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent;
wherein an orthographic projection of a respective connecting line of the plurality of connecting lines on a base substrate intersects with an orthographic projection of at least one row of pixel driving circuits other than the respective pixel driving circuit on the base substrate;
wherein the plurality of connecting lines extend along a direction from the first region to the second region;
wherein multiple first connecting lines of the plurality of connecting lines connect the multiple pixel driving circuits in the first region with multiple corresponding light emitting elements in a third region between the first region and the second region; and
multiple second connecting lines of the plurality of connecting lines connect the multiple light emitting elements in the second region with multiple corresponding pixel driving circuits in the third region.
13. The array substrate of claim 12 , wherein the third region spaces apart the first region and the second region, multiple rows of light emitting elements and transistors of multiple rows of pixel driving circuit are present in the third region.
14. The array substrate of claim 13 , wherein, in the third region, an orthographic projection of an individual light emitting layer of an individual light emitting element of the plurality of light emitting elements on a base substrate at least partially overlaps with an orthographic projection of an individual pixel driving circuit of the plurality of pixel driving circuits on the base substrate, the individual pixel driving circuit being configured to drive light emission in a light emitting element different from the individual light emitting element.
15. The array substrate of claim 13 , wherein, in the third region, an orthographic projection of an individual anode of an individual light emitting element of the plurality of light emitting elements on a base substrate at least partially overlaps with an orthographic projection of an individual pixel driving circuit of the plurality of pixel driving circuits on the base substrate, the individual pixel driving circuit being configured to drive light emission in a light emitting element different from the individual light emitting element.
16. The array substrate of claim 13 , further comprising a plurality of data lines at least partially in the third region and a plurality of data lead lines in the second region, the plurality of data lead lines electrically connecting the plurality of data lines to an integrated circuit;
wherein an orthographic projection of the multiple light emitting elements in the second region on a base substrate at least partially overlaps with an orthographic projection of the plurality of data lead lines on the base substrate.
17. The array substrate of claim 13 , further comprising a peripheral region surrounding a combination of the first region, the second region, and the third region;
wherein the peripheral region comprises a first peripheral sub-region on a first side, a second peripheral sub-region on a second side, a third peripheral sub-region on a third side, and a fourth peripheral sub-region on a fourth side; and
the array substrate further comprises a gate-on-array circuit on at least one of the third peripheral sub-region or the fourth peripheral sub-region.
18. An array substrate, comprising a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements;
wherein, in a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent; and
in a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent;
wherein orthographic projections of any electrically connected pair of pixel driving circuit and light emitting layer on a base substrate are non-overlapping; and
any pair of pixel driving circuit and light emitting layer having overlapping orthographic projections on the base substrate are electrically separated.