IP Library › Granted Patent US 12,242,325
Granted Patent B2
US 12,242,325 · App. 17/708,453 · Granted Mar 4, 2025

Core activation and deactivation for a multi-core processor

Inventors: William Robert Alverson (Del Valle, TX); Amitabh Mehra (Fort Collins, CO); Jerry Anton Ahrens (Sister Bay, WI); Grant Evan Ley (Eden, UT); Anil Harwani (Austin, TX); Joshua Taylor Knight (Georgetown, TX)
Assignee: Advanced Micro Devices, Inc.
G06F1/3287G06F1/3206G06F9/44505
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Quick Facts
Patent No.
US 12,242,325
App. No.
17/708,453
Granted
Mar 4, 2025
Kind
B2
Abstract

Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.

Claims (33)

1. A method comprising:

operating a processor having multiple cores using a core configuration;

receiving a request to switch from the core configuration to a requested core configuration; and

responsive to the request and without rebooting, switching from the core configuration to the requested core configuration by:

signaling the processor to at least one of activate or deactivate one or more cores to obtain the requested core configuration, wherein signaling the processor to deactivate a core is based on falsely indicating in an active core report that the core exceeds a threshold; and

informing an operating system which cores of the processor are signaled activated and deactivated for the requested core configuration using the active core report.

2. The method of claim 1 , further comprising signaling the processor to deactivate one or more cores of the processor without rebooting.

3. The method of claim 1 , further comprising signaling the processor to activate one or more cores of the processor without rebooting.

4. The method of claim 1 , wherein the core configuration has a different number of active cores than the requested core configuration.

5. The method of claim 1 , wherein the core configuration has a different selection of active cores than the requested core configuration.

6. The method of claim 1 , wherein the informing further comprises informing the operating system of a number of active cores.

7. The method of claim 1 , wherein the informing comprises providing the active core report to the operating system, wherein the active core report is formatted according to an Advanced Configuration and Power Interface (ACPI) specification.

8. The method of claim 1 , wherein the informing causes the operating system to provide an indication of the active cores to one or more applications.

9. The method of claim 1 , wherein the informing further comprises informing at least one of the operating system or applications about a branding configuration of the processor corresponding to the requested core configuration.

10. The method of claim 1 , wherein the request is received via user input to a user interface that selects one or more cores to deactivate.

11. The method of claim 1 , wherein the request is received via user input to a user interface that selects one or more cores to activate.

12. The method of claim 1 , wherein the request is received from an application.

13. The method of claim 1 , wherein the operating system includes a scheduler that schedules activated cores to applications and avoids scheduling deactivated cores to applications based on the informing.

14. The method of claim 1 , wherein falsely indicating in the active core report that the core exceeds a threshold comprises falsely indicating in the active core report that the core is hotter than the threshold.

15. A system comprising:

a memory;

a processor having multiple cores; and

a controller configured to, without rebooting, selectively signal to activate and deactivate cores of the processor and inform an operating system which of the cores of the processor are signaled activated and deactivated by using a communication protocol for controlling core operation on a thermal zone basis, wherein signaling to deactivate a core of the processor includes falsely indicating in an active core report that the core is hotter than a threshold.

16. The system of claim 15 , wherein the signaling includes at least one of communicating signals to the processor for power gating or clock gating cores that are to be deactivated.

17. The system of claim 15 , wherein the controller is configured to selectively activate and deactivate the cores of the processor without rebooting by switching from a core configuration to a requested core configuration.

18. The system of claim 15 , wherein the controller is further configured to inform the operating system of a number and selection of active cores of the processor.

19. A method comprising:

displaying a user interface comprising controls for activating or deactivating cores of a processor having multiple cores;

receiving, via the user interface, user input to deactivate one or more cores of the processor; and

deactivating the one or more cores of the processor without rebooting by:

signaling the processor to deactivate the one or more cores based on falsely indicating in an active core report that the one or more cores exceed a threshold; and

informing an operating system which of the multiple cores are signaled deactivated by using the active core report.

20. The method of claim 19 , wherein the user interface comprises controls for activating or deactivating each of the multiple cores of the processor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2022
From: ALVERSON, WILLIAM ROBERT; MEHRA, AMITABH; AHRENS, JERRY ANTON; LEY, GRANT EVAN; HARWANI, ANIL; KNIGHT, JOSHUA TAYLOR
To: ADVANCED MICRO DEVICES, INC
Reel/Frame 059600/0146 →
Continuity (1)
Related Publication 20230315191A1 · Oct 5, 2023
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