Single plate configuration and memory array operation
Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.
1. A method, comprising:
setting a first voltage of a plate that is coupled with a first memory cell and a second memory cell, wherein the first memory cell is coupled with a first digit line;
isolating the first digit line from a second digit line that is coupled with the second memory cell based at least in part on setting the first voltage of the plate;
coupling the plate with the second digit line, wherein the first voltage is applied to the second digit line based at least in part on the coupling and is not applied to the first digit line based at least in part on the isolating; and
applying, based at least in part on coupling the plate with the second digit line and isolating the first digit line from the second digit line, a second voltage to a word line that is coupled with the first memory cell and the second memory cell, and a third voltage to the first digit line.
2. The method of claim 1 , further comprising:
performing an access operation associated with the first memory cell, wherein the plate is set to the first voltage, the plate is coupled with the second digit line, and the second voltage is applied to the word line as part of the access operation, and wherein, after the plate is coupled with the second digit line, the plate and the second digit line operate at a fixed voltage level for a remainder of the access operation.
3. The method of claim 1 , wherein the first memory cell comprises a first selection component and the second memory cell comprises a second selection component, the plate is coupled with the second digit line via a switching component, and the word line is coupled with the first selection component of the first memory cell and the second selection component of the second memory cell.
4. The method of claim 1 , further comprising:
executing a precharge command that comprises:
applying, after applying the second voltage and the third voltage, a fourth voltage to the word line and a fifth voltage to the first digit line.
5. The method of claim 1 , wherein the first digit line is coupled with a third memory cell that comprises a storage element, and wherein a bottom of the storage element is charged based at least in part on applying the third voltage to the first digit line.
6. The method of claim 1 , further comprising:
applying, after applying the second voltage and the third voltage, a fourth voltage to the word line and a fifth voltage to the first digit line; and
maintaining the coupling between the plate and the second digit line after the fourth voltage is applied to the word line and the fifth voltage is applied to the first digit line.
7. The method of claim 6 , further comprising:
applying, before applying the second voltage and the third voltage, a sixth voltage having a negative polarity to the word line, wherein the first voltage applied to the plate has a ground reference voltage, the second voltage applied to the word line has a positive polarity, the third voltage applied to the first digit line has the positive polarity and is smaller than the second voltage, the fourth voltage applied to the word line has the positive polarity and is smaller than the second voltage, and the fifth voltage applied to the first digit line has the ground reference voltage.
8. A method, comprising:
setting a first voltage of a plate that is coupled with a first memory cell and a second memory cell, wherein the first memory cell is coupled with a first digit line;
coupling the plate with a second digit line that is coupled with the second memory cell, wherein the first voltage is applied to the second digit line based at least in part on the coupling;
applying, based at least in part on coupling the plate with the second digit line, a second voltage to a word line that is coupled with the first memory cell and the second memory cell, and a third voltage to the first digit line; and
executing a precharge command that comprises:
applying, after applying the second voltage and the third voltage, a fourth voltage to the word line and a fifth voltage to the first digit line, wherein the fourth voltage has a positive polarity and the fifth voltage has a negative polarity based at least in part on a logic state of the first memory cell, and wherein a storage element of a third memory cell that is coupled with the first digit line is discharged based at least in part on the applying the fifth voltage to the first digit line.
9. A method, comprising:
setting a first voltage of a plate that is coupled with a first memory cell and a second memory cell, wherein the first memory cell is coupled with a first digit line;
coupling the plate with a second digit line that is coupled with the second memory cell, wherein the first voltage is applied to the second digit line based at least in part on the coupling;
applying, based at least in part on coupling the plate with the second digit line, a second voltage to a word line that is coupled with the first memory cell and the second memory cell, and a third voltage to the first digit line; and
executing a precharge command that comprises:
applying, after applying the second voltage and the third voltage, a fourth voltage to the word line and a fifth voltage to the first digit line, wherein the fourth voltage has a positive polarity and the fifth voltage has a ground reference voltage based at least in part on a logic state of the first memory cell, and wherein a storage element of a third memory cell that is coupled with the first digit line remains charged based at least in part on the applying the fifth voltage to the first digit line, the method further comprising:
applying, after executing the precharge command, a sixth voltage to the first digit line having a negative polarity and a seventh voltage to the word line having the negative polarity, wherein the storage element of the third memory cell is discharged based at least in part on applying the sixth voltage to the first digit line.
10. A method, comprising:
executing an activation command for a first memory cell;
setting a first voltage of a plate that is coupled with the first memory cell and a second memory cell, wherein the first memory cell is coupled with a first digit line, and wherein the first voltage is applied to the plate based at least in part on executing the activation command;
coupling the plate with a second digit line that is coupled with the second memory cell, wherein the first voltage is applied to the second digit line based at least in part on the coupling, and wherein the plate is coupled with the second digit line based at least in part on executing the activation command;
applying, based at least in part on coupling the plate with the second digit line, a second voltage to a word line that is coupled with the first memory cell and the second memory cell, and a third voltage to the first digit line, wherein the second voltage is applied to the word line based at least in part on executing the activation command;
executing a sequence comprising read commands, write commands, or both for the first memory cell after executing the activation command;
executing a precharge command based at least in part on a logic state stored by the first memory cell after a last command of the sequence; and
performing, after executing the precharge command, a discharge operation based at least in part on a voltage applied to the first digit line during a precharge operation associated with the precharge command.
11. A method, comprising:
determining, as part of a precharge operation, a logic state of a memory cell that is coupled with a digit line based at least in part on a precharge command;
applying, as part of the precharge operation, a first voltage to the digit line based at least in part on the logic state of the memory cell; and
applying, after a completion of the precharge operation, a second voltage to the digit line that is different than the first voltage based at least in part on the logic state of the memory cell, wherein:
the first voltage has a negative polarity and the second voltage has a ground reference voltage based at least in part on determining the logic state of the memory cell is associated with a first logic value; or
the first voltage has the ground reference voltage and the second voltage has the negative polarity based at least in part on determining the logic state of the memory cell is associated with a second logic value.
12. The method of claim 11 , further comprising:
performing a discharge operation after the completion of the precharge operation, wherein the second voltage is applied to the digit line as part of the discharge operation.
13. The method of claim 11 , wherein the memory cell is coupled with a word line, the method further comprising:
applying, after the completion of the precharge operation, a third voltage to the word line that has the negative polarity.
14. A method, comprising:
determining, as part of a precharge operation, a logic state of a memory cell that is coupled with a digit line based at least in part on a precharge command;
applying, as part of the precharge operation, a first voltage to the digit line based at least in part on the logic state of the memory cell;
writing the logic state determined for the memory cell back to the memory cell based at least in part on the first voltage being applied to the digit line during the precharge operation; and
applying, after a completion of the precharge operation, a second voltage to the digit line that is different than the first voltage based at least in part on the logic state of the memory cell, wherein a second memory cell that is coupled with the digit line is discharged based at least in part on applying one of the first voltage or the second voltage to the digit line.
15. A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
set a first voltage of a plate that is coupled with a first memory cell and a second memory cell, wherein the first memory cell is coupled with a first digit line;
isolate the first digit line from a second digit line that is coupled with the second memory cell based at least in part on setting the first voltage of the plate;
couple the plate with the second digit line, wherein the first voltage is applied to the second digit line based at least in part on the coupling and is not applied to the first digit line based at least in part on the isolating; and
apply, based at least in part on coupling the plate with the second digit line and isolating the first digit line from the second digit line, a second voltage to a word line that is coupled with the first memory cell and the second memory cell, and a third voltage to the first digit line.
16. The memory system of claim 15 , wherein the one or more controllers are further configured to cause the memory system to:
perform an access operation associated with the first memory cell, wherein the plate is set to the first voltage, the plate is coupled with the second digit line, and the second voltage is applied to the word line as part of the access operation, and wherein, after the plate is coupled with the second digit line, the plate and the second digit line operate at a fixed voltage level for a remainder of the access operation.
17. The memory system of claim 15 , wherein the first memory cell comprises a first selection component and the second memory cell comprises a second selection component, the plate is coupled with the second digit line via a switching component, and the word line is coupled with the first selection component of the first memory cell and the second selection component of the second memory cell.
18. The memory system of claim 15 , wherein the one or more controllers are further configured to cause the memory system to:
execute a precharge command that comprises:
applying, after applying the second voltage and the third voltage, a fourth voltage to the word line and a fifth voltage to the first digit line.
19. A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to:
set a first voltage of a plate that is coupled with a first memory cell and a second memory cell, wherein the first memory cell is coupled with a first digit line;
isolate the first digit line from a second digit line that is coupled with the second memory cell based at least in part on setting the first voltage of the plate;
couple the plate with the second digit line, wherein the first voltage is applied to the second digit line based at least in part on the coupling and is not applied to the first digit line based at least in part on the isolating; and
apply, based at least in part on coupling the plate with the second digit line and isolating the first digit line from the second digit line, a second voltage to a word line that is coupled with the first memory cell and the second memory cell, and a third voltage to the first digit line.