Semiconductor device comprising interconnect structures
View Patent ↗A system substrate package, a system package, and methods of forming the same are described herein. The system substrate package includes an integrated substrate with multiple discrete interconnect structures. In embodiments the multiple discrete interconnect structures are placed and encapsulated and have a gap formed between the multiple discrete interconnect structures. The system substrate package reduces package warpage and mitigates board level reliability issues.
1. A semiconductor package comprising:
a redistribution structure;
a first interconnect structure electrically connected to a first side of the redistribution structure;
a second interconnect structure electrically connected to the first side of the redistribution structure, wherein the second interconnect structure is spaced apart from the first interconnect structure by a first region, wherein the second interconnect structure comprises a first sidewall facing the first interconnect structure;
a molded underfill material located within the first region and a second region outside the first region, wherein the molded underfill material has a first height within the first region and a second height within the second region, wherein the first height is smaller than the second height, wherein the first sidewall of the second interconnect structure is only partially covered by the molded underfill material, wherein the molded underfill material within the first region is in physical contact with the first side of the redistribution structure, wherein the molded underfill material has a vertical sidewall within the second region, wherein the vertical sidewall has an interface with a protection layer of the first interconnect structure;
a semiconductor device electrically connected to a second side of the redistribution structure opposite the first interconnect structure; and
an external electrical connector disposed on a surface of the first interconnect structure facing away from the redistribution structure, wherein a first distance between a first end of the external electrical connector and the first side of the redistribution structure is smaller than the second height, and a second distance between a second end of the external electrical connector and the first side of the redistribution structure is greater than the second height, wherein the external electrical connector comprises contact bumps or solder balls.
2. The semiconductor package of claim 1 , wherein the semiconductor package is a system on integrated substrate package.
3. The semiconductor package of claim 1 , wherein the vertical sidewall has an interface with a routing layer of the first interconnect structure.
4. The semiconductor package of claim 3 , wherein the vertical sidewall has an interface with a core substrate of the first interconnect structure, wherein the molded underfill material within the first region is not in physical contact with the routing layer of the first interconnect structure.
5. The semiconductor package of claim 1 , wherein the second interconnect structure further comprises a second sidewall facing away from the first interconnect structure, wherein the molded underfill material covers all of the second sidewall.
6. The semiconductor package of claim 1 , wherein the first interconnect structure further comprises a core substrate and a dielectric layer on a surface of the core substrate facing away from the redistribution structure, wherein a sidewall of the dielectric layer is aligned with a sidewall of the core substrate.
7. A semiconductor package comprising:
a redistribution structure;
a first interconnect structure electrically connected to a first side of the redistribution structure, wherein the first interconnect structure further comprises a core substrate and a protection layer, and the protection layer is on a side of the core substrate facing away from the redistribution structure;
first conductive connectors disposed on a side of the first interconnect structure facing away from the redistribution structure;
a second interconnect structure electrically connected to the first side of the redistribution structure, wherein the second interconnect structure is spaced apart from the first interconnect structure;
second conductive connectors disposed on a side of the second interconnect structure facing away from the redistribution structure; and
a molded underfill material located at least partially between the first interconnect structure and the second interconnect structure, wherein the molded underfill material partially covers a first sidewall of the first interconnect structure adjacent the second interconnect structure and completely covers a second sidewall of the first interconnect structure facing away from the second interconnect structure, wherein the protection layer has a third sidewall in contact with the molded underfill material and a fourth sidewall spaced apart from the molded underfill material.
8. The semiconductor package of claim 7 , further comprising a semiconductor device electrically connected to a second side of the redistribution structure opposite the first interconnect structure.
9. The semiconductor package of claim 7 , further comprising a ring structure disposed over a second side of the redistribution structure opposite the first interconnect structure.
10. The semiconductor package of claim 7 , further comprising a support substrate attached to the first conductive connectors and the second conductive connectors.
11. The semiconductor package of claim 10 , wherein the support substrate has a width greater than a width of the redistribution structure.
12. The semiconductor package of claim 7 , wherein the first interconnect structure comprises a routing layer, wherein the routing layer has a third sidewall in contact with the molded underfill material and a fourth sidewall spaced apart from the molded underfill material.
13. A semiconductor package comprising:
a redistribution structure;
a first interconnect structure in electrical connection to a first side of the redistribution structure, wherein the first interconnect structure comprises a first core substrate and a first routing structure on a side of the first core substrate facing away from the redistribution structure;
a second interconnect structure in electrical connection to the first side of the redistribution structure, wherein the second interconnect structure comprises a second core substrate and a second routing structure on a side of the second core substrate facing away from the redistribution structure, wherein the second interconnect structure is spaced apart from the first interconnect structure, wherein the first routing structure of the first interconnect structure has a first sidewall adjacent to the second interconnect structure and a second sidewall facing away from the second interconnect structure, wherein the first core substrate has a third sidewall aligned with the first sidewall of the first routing structure and a fourth sidewall aligned with the second sidewall of the first routing structure; and
a molded underfill material around the first interconnect structure and over the redistribution structure, wherein the molded underfill material covers the second sidewall of the first routing structure without covering the first sidewall of the first routing structure.
14. The semiconductor package of claim 13 , further comprising a semiconductor device electrically connected to a second side of the redistribution structure opposite the first interconnect structure.
15. The semiconductor package of claim 13 , further comprising a ring structure disposed over a second side of the redistribution structure opposite the first interconnect structure.
16. The semiconductor package of claim 13 , further comprising a semiconductor device and a ring structure disposed over a second side of the redistribution structure opposite the first interconnect structure, wherein the semiconductor device is laterally surrounded by the ring structure.
17. The semiconductor package of claim 13 , wherein the third sidewall of the first core substrate is partially covered by the molded underfill material.
18. The semiconductor package of claim 16 , wherein a sidewall of the second core substrate is partially covered by the molded underfill material.
19. The semiconductor package of claim 13 , wherein the first routing structure further comprises a dielectric layer and a routing layer in the dielectric layer, wherein the dielectric layer comprises at least one sidewall covered by the molded underfill material and at least one sidewall not covered by the molded underfill material.