IP Library › Granted Patent US 12,249,566
Granted Patent B1
US 12,249,566 · App. 18/516,039 · Granted Mar 11, 2025

3DIC with gap-fill structures and the method of manufacturing the same

Inventors: Ping-Jung Wu (Hsinchu, TW); Ken-Yu Chang (Hsinchu, TW); Hao-Wen Ko (Hsinchu, TW); Tsang-Jiuh Wu (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L23/49827H01L21/76837H01L21/76843H01L23/5384H01L27/0688
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Quick Facts
Patent No.
US 12,249,566
App. No.
18/516,039
Granted
Mar 11, 2025
Kind
B1
Abstract

A method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. The gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. The method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.

Claims (44)

1. A method comprising:

bonding a top die to a bottom die;

depositing a first dielectric liner on the top die;

depositing a gap-fill layer on the first dielectric liner, wherein the gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide, wherein the depositing the gap-fill layer comprises:

depositing a first sub layer comprising a first material; and

depositing a second sub layer over the first sub layer, wherein the second sub layer comprises a second material different from the first material;

etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, wherein the etching the gap-fill layer comprises etching the second sub layer, with the first sub layer being used as an etch stop layer;

depositing a second dielectric liner lining the through-opening;

filling the through-opening with a conductive material to form a through-via connecting to the metal pad; and

forming a redistribution structure over and electrically connecting to the top die and the through-via.

2. The method of claim 1 , wherein a first one of the first sub layer and the second sub layer comprises amorphous silicon, and a second one of the first sub layer and the second sub layer comprises a dielectric material.

3. The method of claim 1 , wherein the gap-fill layer comprises a first plurality of sub layers and a second plurality of sub layers stacked alternatingly, wherein the first plurality of sub layers comprise the first material, and the second plurality of sub layers comprise the second material.

4. The method of claim 1 , wherein the etching the gap-fill layer is performed through a Bosch process.

5. The method of claim 1 , wherein the etching the gap-fill layer is performed without stopping until the first dielectric liner is exposed.

6. The method of claim 1 , wherein the depositing the gap-fill layer comprises depositing an amorphous silicon layer.

7. The method of claim 1 , wherein the depositing the gap-fill layer comprises depositing an amorphous silicon-based dielectric layer.

8. The method of claim 1 , wherein the depositing the gap-fill layer comprises depositing a III-V compound semiconductor layer.

9. The method of claim 1 , wherein the depositing the gap-fill layer comprises:

depositing a third sub layer over the second sub layer, wherein the third sub layer comprises a third material different from the second material.

10. The method of claim 9 , wherein the third material is same as the first material.

11. The method of claim 1 , wherein the through-via comprises a lateral protrusion.

12. A method comprising:

bonding a top die over a bottom die, wherein the top die comprises a top metal pad;

forming a dielectric liner comprising a vertical portion on sidewalls of the top die, and a horizontal portion on the bottom die;

depositing a gap-fill layer overlapping the horizontal portion of the dielectric liner, wherein the gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon dioxide;

forming a through-via penetrating through the dielectric liner and the gap-fill layer, wherein the through-via contacts the top metal pad, and wherein the through-via comprises a plurality of lateral protrusions; and

forming a redistribution structure over and electrically coupling to the top die and the through-via.

13. The method of claim 12 , wherein the depositing the gap-fill layer comprises depositing an amorphous silicon-based dielectric material.

14. The method of claim 12 , wherein the depositing the gap-fill layer comprises depositing a semiconductor material.

15. The method of claim 12 , wherein the depositing the gap-fill layer comprises:

depositing a first sub layer comprising a first material; and

depositing a second sub layer over the first sub layer, wherein the second sub layer comprises a second material different from the first material.

16. The method of claim 15 , wherein a first one of the first sub layer and the second sub layer comprises a semiconductor, and a second one of the first sub layer and the second sub layer comprises a dielectric material.

17. The method of claim 12 , wherein the gap-fill layer comprises:

a first plurality of sub layers comprising a same first dielectric material; and

a second plurality of sub layers comprising a same second dielectric materials different from the same first dielectric material, wherein the first plurality of sub layers and the second plurality of sub layers are allocated alternatingly.

18. A method comprising:

bonding a top die over a bottom die;

depositing a first dielectric liner comprising a first portion on sidewalls of the top die, and a second portion on a top surface of the bottom die;

forming a gap-fill layer contacting the first dielectric liner, wherein the forming the gap-fill layer comprises depositing a first sub layer comprising amorphous silicon;

forming a through-via penetrating through the first dielectric liner and the gap-fill layer; and

forming a second dielectric liner, wherein the second dielectric liner encircles the through-via, and wherein the second dielectric liner electrically insulates the through-via from the gap-fill layer.

19. The method of claim 18 , wherein the through-via comprises a plurality of lateral protrusions.

20. The method of claim 18 , wherein the forming the gap-fill layer further comprises forming a second sub layer contacting the first sub layer, and wherein the second sub layer is formed of a different material than the first sub layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2023
From: WU, PING-JUNG; CHANG, KEN-YU; KO, HAO-WEN; WU, TSANG-JIUH
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 065635/0843 →
Continuity (1)
Provisional Application 63520705 · Aug 21, 2023
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