IP Library Granted Patent US 12,249,654
Granted Patent B2
US 12,249,654 · App. 18/447,400 · Granted Mar 11, 2025

Semiconductor device

Inventors: Yohei Yamaguchi (Tokyo, JP); Yuichiro Hanyu (Tokyo, JP); Hiroki Hidaka (Tokyo, JP)
Assignee: Japan Display Inc.
H01L29/7869H01L21/02266H01L21/02554H01L27/1225H01L27/124H01L27/1251H01L29/42384H01L29/78648H01L29/78696H10K59/126
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Quick Facts
Patent No.
US 12,249,654
App. No.
18/447,400
Granted
Mar 11, 2025
Kind
B2
Abstract

A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.

Claims (25)

1. A semiconductor device comprising:

an oxide semiconductor layer;

a gate electrode opposing the oxide semiconductor layer;

a gate insulating layer between the oxide semiconductor layer and the gate electrode;

a first insulating layer covering the oxide semiconductor layer;

an oxide layer;

a first conductive layer above the first insulating layer; and

a first electrode arranged above the oxide semiconductor layer and electrically connecting with the oxide semiconductor layer,

wherein

the oxide layer is arranged between the first insulating layer and the first conductive layer, and directly contacting the first insulating layer and the first conductive layer,

the first insulating layer have a first opening,

the first insulating layer directly contacts the oxide semiconductor layer,

the oxide layer has a second opening overlapping the first opening in a plan view,

the first conductive layer is arranged in the first opening and the second opening and directly contacts the first electrode at a bottom part of the first opening,

the gate electrode is arranged below the oxide semiconductor layer,

the oxide layer does not overlap the oxide semiconductor layer and the gate electrode, and

the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plane view.

2. The semiconductor device according to claim 1 , wherein

the first insulating layer is an oxide insulating layer,

the oxide layer is an oxide insulating layer with the same composition as the first insulating layer, and

a composition ratio of oxygen in the oxide layer is larger than a composition ratio of oxygen in the first insulating layer.

3. The semiconductor device according to claim 1 , wherein

the first conductive layer contacts the oxide layer at a side wall of the second opening.

4. The semiconductor device according to claim 1 , wherein

a pattern of the oxide layer is substantially a same pattern as a pattern of the first conductive layer in a plan view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
Priority Claims (1)
JP 2019-002939 · Jan 10, 2019 · national
Continuity (3)
Continuation 17510534 · Oct 26, 2021
Continuation 16735800 · Jan 7, 2020
Related Publication 20230387319A1 · Nov 30, 2023
References Cited (2)
US 10032888B2 · Tanaka · 2018 [cited by examiner]
US 20160056043A1 · Tanaka · 2016 [cited by examiner]