IP Library › Granted Patent US 12,253,924
Granted Patent B2
US 12,253,924 · App. 18/318,283 · Granted Mar 18, 2025

Error rate measurement apparatus and error rate measurement method

Inventor: Hiroyuki Onuma (Kanagawa, JP)
Assignee: ANRITSU CORPORATION
G06F11/221G06F11/2268G06F11/2733G06F11/326
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Quick Facts
Patent No.
US 12,253,924
App. No.
18/318,283
Granted
Mar 18, 2025
Kind
B2
Abstract

An error rate measurement apparatus includes an operation display unit and a display control unit. Displays a measurement result when the matrix scan function is executed. The display control unit displays a first coefficient value in a selectable manner by tabs of a number corresponding to the Full Swing value, uses each one of combinations of the first coefficient value, each second coefficient value, and each third coefficient value on the selected table as the cell, displays an error count value and the bit error rate for each cell, which are obtained by the matrix scan function on a display screen in a matrix, and identifies and displays the bit error rate for each cell on the display screen according to an error degree.

Claims (27)

1. An error rate measurement apparatus that executes a matrix scan function for measuring a bit error rate by transmitting a test signal by a combination of coefficient values in a Full Swing value defined by a PCI Express standard to a device under test (W) during link training, and receiving a measurement target signal returned back from the device under test in response to transmission of the test signal, wherein

the test signal is based on a parameter value of a cell as a scanning target selected and set from a triangular matrix by the combination of the coefficient values,

three types of coefficient values are provided in the Full Swing value, and

the error rate measurement apparatus comprises:

a display control unit that displays a first coefficient value in a selectable manner by tabs of a number corresponding to the Full Swing value, uses each one of combinations of the first coefficient value, each second coefficient value, and each third coefficient value on the selected tab as the cell, displays an error count value and the bit error rate for each cell, which are obtained by the matrix scan function on a display screen in a matrix, and identifies and displays the bit error rate for each cell on the display screen, according to an error degree.

2. The error rate measurement apparatus according to claim 1 , wherein

the first coefficient value is set as C −2 ,

each second coefficient value is set as C +1 ,

each third coefficient value is set as C −1 , and

the display control unit displays a thumbnail image on the display screen as a reduced image in which the bit error rate for each cell is color-coded according to the error degree.

3. The error rate measurement apparatus according to claim 2 , wherein

the display control unit uses C +1 and C −1 as a combination of a horizontal direction coordinate axis and a vertical direction coordinate axis, uses C −2 as a depth direction coordinate axis, and displays C −2 , C −1 , and C +1 on the display screen in a three-dimensional bird-eye view.

4. An error rate measurement method for executing a matrix scan function for measuring a bit error rate by transmitting a test signal by a combination of coefficient values in a Full Swing value defined by a PCI Express standard to a device under test (W) during link training, and receiving a measurement target signal returned back from the device under test in response to transmission of the test signal, wherein

the test signal is based on a parameter value of a cell as a scanning target selected and set from a triangular matrix by the combination of the coefficient values,

three types of coefficient values are provided in the Full Swing value, and

the error rate measurement method comprises:

a step of displaying a first coefficient value in a selectable manner by tabs of a number corresponding to the Full Swing value;

a step of using each one of combinations of the first coefficient value, each second coefficient value, and each third coefficient value on the selected tab as the cell, and displaying an error count value and the bit error rate for each cell, which are obtained by the matrix scan function on a display screen in a matrix; and

a step of identifying and displaying the bit error rate for each cell on the display screen, according to an error degree.

5. The error rate measurement method according to claim 4 , wherein

the first coefficient value is set as C −2 ,

each second coefficient value is set as C +1 ,

each third coefficient value is set as C −1 , and

the error rate measurement method further comprises:

a step of displaying a thumbnail image on the display screen as a reduced image in which the bit error rate for each cell is color-coded according to the error degree.

6. The error rate measurement method according to claim 5 , further comprising:

a step of using C +1 and C −1 as a combination of a horizontal direction coordinate axis and a vertical direction coordinate axis, using C −2 as a depth direction coordinate axis, and displaying C −2 , C −1 , and C +1 on the display screen in a three-dimensional bird-eye view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2023
From: ONUMA, HIROYUKI
To: ANRITSU CORPORATION
Reel/Frame 063657/0542 →
Priority Claims (1)
JP 2022-125666 · Aug 5, 2022 · national
Continuity (1)
Related Publication 20240045778A1 · Feb 8, 2024
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