Storage device and operating method thereof
A storage device is provided. The storage device includes: a first non-volatile memory including a plurality of cell strings storing a plurality of logical address values and a plurality of physical address values; a second non-volatile memory including a plurality of memory cells corresponding to the plurality of physical address values; and a storage controller configured to read a first physical address value from the first non-volatile memory based on a first logical address value, and control a read operation on the second non-volatile memory based on the first physical address value. A first cell string among the plurality of cell strings includes: a plurality of first memory cells storing the first logical address value and respectively connected to word lines in a first group; and at least one second memory cell storing the first physical address value and connected to at least one word line in a second group.
1. A storage device comprising:
a first non-volatile memory comprising a plurality of cell strings storing a plurality of logical address values and a plurality of physical address values;
a second non-volatile memory comprising a plurality of memory cells corresponding to the plurality of physical address values; and
a storage controller configured to read a first physical address value from the first non-volatile memory based on a first logical address value, and control a read operation on the second non-volatile memory based on the first physical address value,
wherein a first cell string among the plurality of cell strings comprises:
a plurality of first memory cells storing the first logical address value and respectively connected to word lines in a first group, and
at least one second memory cell storing the first physical address value and connected to at least one word line in a second group.
2. The storage device of claim 1 , wherein the first non-volatile memory is configured to:
search for the first cell string storing the first logical address value among the plurality of cell strings by applying, to the word lines in the first group, word line voltages corresponding to the first logical address value, and
read the first physical address value by performing the read operation on the at least one second memory cell while current flows in the first cell string due to the word line voltages.
3. The storage device of claim 1 , wherein the plurality of first memory cells comprise a plurality of first single-level cells storing encoded data of the first logical address value,
wherein the at least one second memory cell comprises a multi-level cell storing the first physical address value, and
wherein the multi-level cell is configured to store at least two bits of data.
4. The storage device of claim 1 , wherein the plurality of first memory cells comprise a plurality of first single-level cells storing encoded data of the first logical address value, and
wherein the at least one second memory cell comprises a plurality of second single-level cells storing encoded data of the first physical address value.
5. The storage device of claim 1 , wherein a second cell string among the plurality of cell strings comprises:
a plurality of third memory cells storing the first logical address value and respectively connected to the word lines in the first group; and
at least one fourth memory cell connected to the at least one word line in the second group, and
wherein the at least one second memory cell and the at least one fourth memory cell correspond to the first physical address value.
6. The storage device of claim 1 , wherein the first non-volatile memory further comprises a row decoder configured to respectively apply, to the word lines in the first group, word line voltages corresponding to the first logical address value.
7. The storage device of claim 1 , wherein the first non-volatile memory further comprises a control logic circuit configured to generate data by encoding the first logical address value.
8. The storage device of claim 7 , wherein the control logic circuit is further configured to:
receive the first logical address value in decimal from the storage controller,
convert the first logical address value into a first value in binary, and
generate the data by encoding “0” in the first value into “01” and encoding “1” in the first value into “10”.
9. The storage device of claim 7 , wherein the control logic circuit is further configured to:
receive the first logical address value in binary from the storage controller, and
generate the data by encoding “0” in the first logical address value into “01” and encoding “1” in the first logical address value into “10”.
10. The storage device of claim 1 , wherein the first non-volatile memory further comprises a page buffer configured to buffer the first physical address value read from the at least one second memory cell.
11. The storage device of claim 1 , wherein the first cell string further comprises at least one third memory cell storing validity information indicating whether a mapping relationship between the first logical address value and the first physical address value is valid.
12. The storage device of claim 1 , wherein, the storage controller is further configured to update a physical address corresponding to the first logical address value to a second physical address value so that a second cell string among the plurality of cell strings comprises:
a plurality of third memory cells storing the first logical address value; and
at least one fourth memory cell storing the second physical address value.
13. The storage device of claim 1 , further comprising a buffer chip between the storage controller and the first and second non-volatile memories,
wherein the first non-volatile memory comprises a first memory chip,
wherein the second non-volatile memory comprises a plurality of second memory chips, and
wherein the buffer chip is configured to receive the first logical address value from the storage controller, transmit the first logical address value to the first memory chip, receive the first physical address value from the first memory chip and transmit the first physical address value to one of the plurality of second memory chips.
14. A storage device comprising:
a first non-volatile memory comprising a plurality of cell strings storing a plurality of logical address values and a plurality of physical address values;
a second non-volatile memory comprising a plurality of memory cells corresponding to the plurality of physical address values; and
a storage controller configured to read a first logical address value from the first non-volatile memory based on a first physical address value, and control a read operation on the second non-volatile memory based on the first physical address value,
wherein a first cell string among the plurality of cell strings comprises:
a plurality of first memory cells storing the first physical address value and respectively connected to word lines in a first group, and
at least one second memory cell storing the first logical address value and connected to at least one word line in a second group.
15. The storage device of claim 14 , wherein the plurality of first memory cells comprise a plurality of first single-level cells storing encoded data of the first physical address value,
wherein the at least one second memory cell comprises a multi-level cell storing the first logical address value, and
wherein the multi-level cell is configured to store at least two bits of data.
16. The storage device of claim 14 , wherein the plurality of first memory cells comprise a plurality of first single-level cells storing encoded data of the first physical address value, and
wherein the at least one second memory cell comprises a plurality of second single-level cells storing encoded data of the first logical address value.
17. The storage device of claim 14 , further comprising a buffer chip between the storage controller and the first and second non-volatile memories,
wherein the first non-volatile memory comprises a first memory chip,
wherein the second non-volatile memory comprises a plurality of second memory chips, and
wherein the buffer chip is configured to receive the first physical address value from the storage controller, transmit the first physical address value to the first memory chip and receive the first logical address value from the first memory chip.
18. A non-volatile memory device comprising:
a control logic circuit configured to generate data by encoding a first logical address value received from a controller;
a row decoder configured to respectively apply, to word lines in a first group, word line voltages corresponding to the first logical address value; and
a memory cell array comprising a plurality of cell strings storing a plurality of logical address values and a plurality of physical address values,
wherein a first cell string among the plurality of cell strings comprises:
a plurality of first memory cells storing the first logical address value and respectively connected to the word lines in the first group, and
at least one second memory cell storing a first physical address value mapped to the first logical address value and connected to at least one word line in a second group, and
wherein the first physical address value is read by a read operation performed on the at least one second memory cell while current flows in the first cell string due to the word line voltages.
19. The non-volatile memory device of claim 18 , wherein the plurality of first memory cells comprises a plurality of first single-level cells storing encoded data of the first logical address value,
wherein the at least one second memory cell comprises a multi-level cell storing the first physical address value, and
wherein the multi-level cell is configured to store at least two bits of data.
20. The non-volatile memory device of claim 18 , wherein the plurality of first memory cells comprise a plurality of first single-level cells storing encoded data of the first logical address value, and
wherein the at least one second memory cell comprises a plurality of second single-level cells storing encoded data of the first physical address value.