Hierarchical hybrid network on chip architecture for compute-in-memory probabilistic machine learning accelerator
Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.
1. An apparatus for a network on a chip (NoC), the apparatus comprising:
a plurality of supertiles, each supertile including an analog router and a plurality of compute-in-memory tiles; and
logic circuitry, at least a portion of which is implemented in a first analog router of a first supertile of the plurality of supertiles, the logic circuitry to:
receive a first analog output from a first compute-in-memory tile of a first plurality of compute-in-memory tiles of the first supertile, the first analog output representing a weight of a neural network to be executed on the NoC;
determine, based on a configuration of the neural network, that a destination of the first analog output identifies a second supertile of the plurality of supertiles;
generate, by a Gaussian distribution circuit of the analog router, a Gaussian distribution for the weight:
convert, by an analog-to-digital converter (ADC) of the analog router, the first analog output to a first digital output; and
transmit, by the analog router, the first digital output including the Gaussian distribution to the second supertile via at least one digital router of a communications bus of the NoC, the communications bus including a plurality of digital routers.
2. The apparatus of claim 1 , wherein the logic circuitry is to perform, by the Gaussian distribution circuit, a stochastic rounding operation on the weight.
3. The apparatus of claim 1 , wherein the destination is a first destination, and the logic circuitry is to:
receive, by the analog router, a second analog output of the first compute-in-memory tile;
determine, by the analog router, that a second destination of the second analog output identifies a second compute-in-memory tile of the first plurality of compute-in-memory tiles of the first supertile; and
transmit, by the analog router, the second analog output to the second compute-in-memory tile.
4. The apparatus of claim 3 , wherein the weight is a first weight, the second analog output represents a second weight of the neural network, the Gaussian distribution is a first Gaussian distribution, and the logic circuitry is to:
generate, by the Gaussian distribution circuit of the analog router, a second Gaussian distribution for the second weight; and
transmit, by the analog router to the second compute-in-memory tile, the second Gaussian distribution and the second analog output.
5. An apparatus for a network on a chip (NoC), the apparatus comprising:
a plurality of supertiles, each supertile including an analog router and a plurality of compute-in-memory tiles; and
logic circuitry, at least a portion of which is implemented in a first analog router of a first supertile of the plurality of supertiles, the logic circuitry to:
receive a first analog output from a first compute-in-memory tile of a first plurality of compute-in-memory tiles of the first supertile;
determine, based on a configuration of a neural network to be executed on the NoC, that a destination of the first analog output identifies a second supertile of the plurality of supertiles;
convert, by an analog-to-digital converter (ADC) of the analog router, the first analog output to a first digital output;
transmit, by the analog router, the first digital output to the second supertile via a communications bus of the NoC;
receive, by the analog router via a digital router of the communications bus, a digital packet from the second supertile;
convert, by a digital-to-analog converter (DAC) of the analog router, the digital packet to an analog signal; and
provide, by the analog router, the analog signal to one of the first plurality of compute-in-memory tiles of the first supertile.
6. The apparatus of claim 1 , wherein each of the plurality of compute-in-memory tiles includes processor circuitry and a memory, and the logic circuitry is to packetize the first digital output into one or more packets prior to transmission of the first digital output to the second supertile.
7. A non-transitory computer-readable storage medium comprising instructions that cause a network on a chip (NoC) to:
receive, by an analog router of a first supertile of a plurality of supertiles of the NoC, a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile, the first analog output including a weight of a neural network to be executed on the NoC;
determine, by the analog router and based on a configuration of the neural network, that a destination of the first analog output identifies a second supertile of the plurality of supertiles;
convert, by an analog-to-digital converter (ADC) of the analog router, the first analog output to a first digital output;
transmit, by the analog router, the first digital output to the second supertile via a communications bus of the NoC;
receive, by the analog router via a digital router of the communications bus, a digital packet from the second supertile;
convert, by a digital-to-analog converter (DAC) of the analog router, the digital packet to an analog signal; and
provide, by the analog router, the analog signal to one of the plurality of compute-in- memory tiles of the first supertile.
8. The non-transitory computer-readable storage medium of claim 7 , wherein the instructions cause the NoC to:
generate, by a Gaussian distribution circuit of the analog router, a Gaussian distribution for the weight; and
transmit, by the analog router, the first digital output to the second supertile via at least one digital router of a plurality of digital routers of the communications bus, the first digital output including the Gaussian distribution.
9. The non-transitory computer-readable storage medium of claim 8 , wherein the instructions cause the NoC to perform, by the Gaussian distribution circuit, a stochastic rounding operation on the weight.
10. The non-transitory computer-readable storage medium of claim 7 , wherein the destination is a first destination, and the instructions cause the NoC to:
receive, by the analog router, a second analog output of the first compute-in-memory tile;
determine, by the analog router, that a second destination of the second analog output identifies a second compute-in-memory tile of the plurality of compute-in-memory tiles of the first supertile; and
transmit, by the analog router, the second analog output to the second compute-in-memory tile.
11. The non-transitory computer-readable storage medium of claim 10 , wherein the instructions cause the NoC to:
generate, by a Gaussian distribution circuit of the analog router, a Gaussian distribution for the weight; and
transmit, by the analog router to the second compute-in-memory tile, the Gaussian distribution and the second analog output via at least one digital router of a plurality of digital routers of the NoC.
12. The non-transitory computer-readable storage medium of claim 7 , wherein each of the plurality of compute-in-memory tiles includes processor circuitry and a memory, and the instructions cause the NoC to packetize the first digital output into one or more packets prior to transmission of the first digital output to the second supertile.
13. An apparatus comprising:
means for routing to:
receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of a first supertile of a plurality of supertiles of a network on a chip (NoC), the first analog output to represent a weight of a neural network to be executed on the NoC;
determine, based on a configuration of the neural network, that a destination of the first analog output identifies a second supertile of the plurality of supertiles;
transmit a first digital output to the second supertile via a communications bus of the NoC:
receive, from a digital router of the communications bus, a digital packet from the second supertile; and
provide an analog signal to one of the plurality of compute-in-memory tiles of the first supertile;
means for converting the first analog output to the first digital output; and
means for converting the digital packet to the analog signal.
14. The apparatus of claim 13 , wherein the apparatus further includes including means for generating a Gaussian distribution for the weight, and the means for routing is to transmit the first digital output to the second supertile via at least one digital router of a plurality of digital routers of the communications bus, the first digital output including the Gaussian distribution.
15. The apparatus of claim 14 , further including means for performing a stochastic rounding operation on the weight.
16. The apparatus of claim 13 , wherein the destination is a first destination, and the means for routing is to:
receive a second analog output of the first compute-in-memory tile;
determine that a second destination of the second analog output identifies a second compute-in-memory tile of the plurality of compute-in-memory tiles of the first supertile; and
transmit the second analog output to the second compute-in-memory tile.
17. The apparatus of claim 16 , wherein the apparatus further includes means for generating a Gaussian distribution for the weight, and the means for routing is to transmit the Gaussian distribution and the second analog output to the second compute-in-memory tile.