Granted Patent B2

US 12,255,100 · App. 18/361,717 · Granted Mar 18, 2025

Inventors: Shahaji B. More (Hsinchu, TW); Chandrashekhar Prakash Savant (Hsinchu, TW)

Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.

H01L21/823412H01L21/0259H01L21/02603H01L21/31111H01L21/823431H01L21/823468H01L27/088H01L27/0886H01L29/0665H01L29/0673H01L29/42392H01L29/66545H01L29/66553H01L29/66742H01L29/785H01L29/78696

Abstract

Claims (39)

1. A method, comprising:

forming an inter-sheet filler layer between first semiconductor nanostructures of a first nanostructure transistor and between second semiconductor nanostructures of a second nanostructure transistor;

removing the inter-sheet filler layer from between the first semiconductor nanostructures and the second semiconductor nanostructures;

forming a first gate metal layer between the first semiconductor nanostructures; and

forming a second gate metal between the second semiconductor nanostructures.

2. The method of claim 1 , wherein the first nanostructure transistor has a first threshold voltage, and the second nanostructure transistor has a second threshold voltage different than the first threshold voltage.

3. The method of claim 1 , further comprising:

forming the inter-sheet filler layer between third semiconductor nanostructures of a third nanostructure transistor;

forming the first gate metal layer while the inter-sheet filler layer is between the third semiconductor nanostructures;

forming the second gate metal layer while the inter-sheet filler layer is between the third semiconductor nanostructures;

removing the first gate metal layer, the second gate metal layer, and the inter-sheet filler layer from the third semiconductor nanostructures; and

forming a third gate metal layer between the third semiconductor nanostructures and on the second gate metal layer over the first and second semiconductor nanostructures.

4. The method of claim 3 , wherein the first nanostructure transistor has a first threshold voltage, the second nanostructure transistor has a second threshold voltage different than the first threshold voltage, and the third nanostructure transistor has a third threshold voltage different than the first and second threshold voltages.

5. The method of claim 1 , further comprising forming a gate dielectric layer on the first and second semiconductor nanostructures prior to forming the inter-sheet filler layer.

6. The method of claim 5 , wherein forming the inter-sheet filler layer between the first and second semiconductor nanostructures includes forming the inter-sheet filler layer on the gate dielectric layer.

7. The method of claim 1 , further comprising removing the inter-sheet filler layer from sides of the first and second semiconductor nanostructures prior to forming the first gate metal layer.

8. The method of claim 7 , wherein removing the inter-sheet filler layer from sides of the first and second semiconductor nanostructures includes performing an anisotropic etch.

9. The method of claim 7 , wherein removing the inter-sheet filler layer from sides of the first and second semiconductor nanostructures includes performing a sidewall conversion treatment on side portions of the inter-sheet filler layer on the sides of the first and second nanostructures and selectively etching the side portions with respect to portions of the inter-sheet filler layer between the first semiconductor nanostructures and between the second semiconductor nanostructures.

10. The method of claim 9 , wherein selectively etching includes performing a wet etch.

11. A method, comprising:

forming an inter-sheet filler layer between first semiconductor nanostructures of a first nanostructure transistor and between second semiconductor nanostructures of a second nanostructure transistor;

removing the inter-sheet filler layer from between the first semiconductor nanostructures;

forming a first gate metal layer between the first semiconductor nanostructures and in contact with inter-sheet filler layer between the second semiconductor nanostructures; and

forming a second gate metal layer on the first gate metal layer on the first and second semiconductor nanostructures.

12. The method of claim 11 , wherein the second gate metal layer is between third semiconductor nanostructures of a third nanostructure transistor.

13. The method of claim 12 , wherein the second gate metal layer is formed after the first gate metal layer has been removed from the third semiconductor nanostructures.

14. The method of claim 11 , wherein the inter-sheet filler layer includes silicon.

15. An integrated circuit, comprising:

a first nanostructure transistor including a plurality of first semiconductor nanostructures;

a second nanostructure transistor including a plurality of second semiconductor nanostructures;

a third nanostructure transistor including a plurality of third semiconductor nanostructures;

an inter sheet filler layer between the second semiconductor nanostructures;

a first gate metal layer substantially filling a space between the first semiconductor nanostructures and in contact with the inter-sheet filler layer; and

a second gate metal layer substantially filling a space between the third semiconductor nanostructures.

16. The integrated circuit of claim 15 , wherein the second gate metal layer is on the first gate metal layer on sides of the first semiconductor nanostructures.

17. The integrated circuit of claim 15 , wherein the gate dielectric has a variation in thickness less than 0.2 nm on the second semiconductor nanostructures.

18. The integrated circuit of claim 15 , wherein the first and second gate metal layers are different materials.

19. The integrated circuit of claim 15 , further comprising a glue layer on the second gate metal layer.

20. The integrated circuit of claim 19 , further comprising a gate fill material on the glue layer.

Continuity (3)

References Cited (19)