Image sensor with overlap of backside trench isolation structure and vertical transfer gate
Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.
1. An image sensor comprising:
a semiconductor substrate having a first side and a second side opposite the first side, the semiconductor substrate including a bulk region and a doped region, the doped region extending from the first side toward the second side of the semiconductor substrate;
a photodetector in the semiconductor substrate;
a transfer gate disposed over the photodetector, the transfer gate having a lateral portion extending over the first side of the semiconductor substrate and having a vertical portion extending from the lateral portion into the semiconductor substrate; and
a trench isolation structure extending from the second side of the semiconductor substrate into the semiconductor substrate along a first sidewall of the bulk region of the semiconductor substrate, a second sidewall of the bulk region of the semiconductor substrate, a sidewall of the doped region of the semiconductor substrate, a lower surface of the doped region of the semiconductor substrate, and a lower surface of the bulk region of the semiconductor substrate, wherein the trench isolation structure laterally surrounds the photodetector and the transfer gate, and wherein an upper surface of the trench isolation structure is above a lower surface of the vertical portion of the transfer gate.
2. The image sensor of claim 1 , wherein the bulk region and the doped region have a same doping type.
3. The image sensor of claim 1 , wherein the lower surface of the vertical portion of the transfer gate is disposed at a first depth below the first side of the semiconductor substrate, the upper surface of the trench isolation structure is disposed at a second depth below the first side of the semiconductor substrate, and the first depth is greater than the second depth.
4. The image sensor of claim 1 , wherein the doped region of the semiconductor substrate extends below the upper surface of the trench isolation structure, and wherein the vertical portion of the transfer gate extends below the doped region of the semiconductor substrate.
5. The image sensor of claim 1 , wherein the trench isolation structure includes a vertical isolation segment that is partially formed by the upper surface of the trench isolation structure, the vertical isolation segment having a first width about a central axis of the vertical isolation segment, wherein the doped region has a vertical doped segment that is partially formed by the sidewall and the lower surface of the doped region, the vertical doped segment having a second width about a central axis of the vertical doped segment, and wherein the central axis of the vertical isolation segment is offset from the central axis of the vertical doped segment.
6. The image sensor of claim 1 , further comprising:
a gate dielectric layer extending from directly between the transfer gate and the semiconductor substrate to over the upper surface of the trench isolation structure.
7. The image sensor of claim 6 , wherein the bulk region of the semiconductor substrate is directly between the gate dielectric layer and the upper surface of the trench isolation structure, and wherein the doped region of the semiconductor substrate is directly between the gate dielectric layer and the upper surface of the trench isolation structure.
8. The image sensor of claim 6 , wherein the gate dielectric layer is directly over the doped region and the upper surface of the trench isolation structure.
9. An image sensor comprising:
a semiconductor substrate having a first side and a second side opposite the first side, the semiconductor substrate including a bulk region, a collector region, and a doped region, the bulk region and the collector region forming a photodetector in the semiconductor substrate, the doped region laterally surrounding the photodetector and extending from the first side to a first depth below the first side of the semiconductor substrate;
a transfer gate disposed over the photodetector, the transfer gate having a lateral portion extending over the first side of the semiconductor substrate and having a vertical portion extending to a second depth below the first side of the semiconductor substrate; and
a trench isolation structure extending from the second side of the semiconductor substrate to a third depth below the first side of the semiconductor substrate, the trench isolation structure laterally surrounding the photodetector, the third depth being less than the second depth so a lower surface of the vertical portion of the transfer gate is below an upper surface of the trench isolation structure, wherein the trench isolation structure has a first sidewall and a second sidewall on opposite sides of the upper surface of the trench isolation structure,
wherein the doped region of the semiconductor substrate is on the first sidewall and the upper surface of the trench isolation structure, and wherein the bulk region of the semiconductor substrate is on the second sidewall and the upper surface of the trench isolation structure.
10. The image sensor of claim 9 , wherein the first depth is greater than the third depth and less than the second depth.
11. The image sensor of claim 9 , wherein the bulk region has a first doping type, the collector region has a second doping type, different than the first doping type, and the doped region has the first doping type.
12. The image sensor of claim 9 , further comprising:
a gate dielectric layer on the lower surface of the vertical portion of the transfer gate and directly over the upper surface of the trench isolation structure.
13. The image sensor of claim 9 , wherein a ratio of the first depth to the second depth ranges from approximately 1.05 to 2.
14. The image sensor of claim 9 , wherein the bulk region borders the doped region along a first interface and the bulk region borders the collector region along a second interface.
15. An image sensor comprising:
a semiconductor substrate having a first side and a second side opposite the first side;
a first photodetector and a second photodetector in the semiconductor substrate, the second photodetector neighboring the first photodetector;
a first transfer gate over the first photodetector and a second transfer gate over the second photodetector, the first transfer gate having a first lateral portion extending over the first side of the semiconductor substrate and having a first vertical portion extending from the first lateral portion to below the first side of the semiconductor substrate, the second transfer gate having a second lateral portion extending over the first side of the semiconductor substrate and having a second vertical portion extending from the second lateral portion to below the first side of the semiconductor substrate;
a doped region in the semiconductor substrate, the doped region extending from the first side toward the second side of the semiconductor substrate and directly between the first transfer gate and the second transfer gate; and
a trench isolation structure directly under the doped region and extending into the semiconductor substrate from the second side of the semiconductor substrate toward the first side of the semiconductor substrate and directly between the first transfer gate and the second transfer gate, wherein an upper surface of the trench isolation structure is above a lower surface of the first vertical portion and a lower surface of the second vertical portion,
wherein a lateral distance between the doped region and the first vertical portion is less than a lateral distance between the trench isolation structure and the first vertical portion, and wherein a lateral distance between the doped region and the second vertical portion is greater than a lateral distance between the trench isolation structure and the second vertical portion.
16. The image sensor of claim 15 , wherein the semiconductor substrate has a first doping type and the doped region has the first doping type.
17. The image sensor of claim 15 , wherein the trench isolation structure has a vertical segment that is delimited by the upper surface of the trench isolation structure and a pair of sidewalls of the trench isolation structure, and wherein a width of the vertical segment is narrower at the upper surface of the trench isolation structure than at the second side of the semiconductor substrate.
18. The image sensor of claim 15 , further comprising:
a first floating diffusion region adjacent to the first transfer gate and a second floating diffusion region adjacent to the second transfer gate, wherein a distance between the doped region and the first floating diffusion region is less than a distance between the doped region and the second floating diffusion region.
19. The image sensor of claim 15 , further comprising:
a floating diffusion region extending between the first transfer gate and the second transfer gate and extending over the doped region.
20. The image sensor of claim 15 , further comprising:
a gate dielectric directly over the upper surface of the trench isolation structure.