Embedded MRAM integrated with super via and dummy fill
A device includes a plurality of magnetic random-access memory (MRAM) cells in a first region of the device; and a dummy MRAM pillar disposed in a second region of the device, wherein the dummy MRAM pillar is not connected to an active metal feature.
1. A device comprising:
a plurality of magnetic random-access memory (MRAM) cells in a first region of the device;
a dummy MRAM pillar disposed in a second region of the device,
wherein the dummy MRAM pillar is not connected to an active metal feature;
a super via disposed in a third region of the device with a sidewall spacer on a sidewall of the super via; and
a residual portion of a sacrificial MRAM stack disposed between the super via and the sidewall spacer.
2. The device of claim 1 , wherein the super via is disposed on a lower metal line and an upper metal line is disposed on the super via.
3. The device of claim 1 , further comprising a metal interconnect disposed in the third region.
4. The device of claim 1 , wherein the dummy MRAM pillar is disposed entirely on an interlevel dielectric.
5. A device comprising:
a plurality of lower metal lines;
a plurality of upper metal lines;
a plurality of magnetic random-access memory (MRAM) cells in a first region of the device and electrically connected to respective ones of the lower metal lines and the upper metal lines;
a super via disposed in a second region of the device and electrically connected to a respective one of the lower metal lines and a respective one of the upper metal lines;
a dummy MRAM pillar disposed in a third region of the device;
a first sidewall spacer on a sidewall of the super via; and
a residual portion of a sacrificial MRAM stack disposed between the super via and the first sidewall spacer.
6. The device of claim 5 , further comprising a first sidewall spacer on a sidewall of the super via.
7. The device of claim 5 , further comprising:
a plurality of second sidewall spacers on sidewalls of the MRAM cells.
8. The device of claim 5 , further comprising a metal line in the second region electrically connected to a respective one of the lower metal lines and a respective one of the upper metal lines.
9. The device of claim 5 , wherein the dummy MRAM pillar is disposed entirely on an interlevel dielectric.
10. The device of claim 5 , wherein the dummy MRAM pillar is capped by an etch stop liner.
11. The device of claim 5 , further comprising:
an etch stop liner with openings exposing upper surfaces of the plurality of MRAM cells and the super via;
a plurality of fully aligned vias disposed between the upper metal lines and the MRAM cells; and
a plurality of bottom electrodes disposed between the lower metal lines and the MRAM cells.
12. The device of claim 7 , further comprising:
a third sidewall spacer on a sidewall of the dummy MRAM pillar.
13. A method of forming a device comprising:
forming a plurality of magnetic random-access memory (MRAM) cells in a first region of the device;
forming a dummy MRAM pillar in a second region of the device;
exposing upper surfaces of the plurality of MRAM cells;
depositing a metal forming a plurality of upper metal lines over the plurality of MRAM cells;
forming a sacrificial MRAM stack in a third region of the device;
forming a first sidewall spacer on a sidewall of the sacrificial MRAM stack; and
removing at least a portion of the sacrificial MRAM stack to form a super via trench exposing a first lower metal line prior to depositing the metal, wherein depositing the metal further comprises:
forming a super via in the super via trench, wherein a residual portion of the sacrificial MRAM stack is disposed between the super via and the first sidewall spacer.
14. The method of claim 13 ,
wherein depositing the metal further comprises:
forming a super via upper metal line over the super via, wherein the super via electrically connects the super via upper metal line to the first lower metal line.
15. The method of claim 14 , further comprising forming a plurality of lower metal lines, including the first lower metal line, disposed in an interlevel dielectric in the first and third regions.
16. The method of claim 15 , further comprising forming a plurality of bottom electrodes contacting each of the lower metal lines in the first region, and at least one, and less than all, of the lower metal lines in the third region.
17. The method of claim 14 , further comprising forming a metal line in the third region, the metal line electrically connected to a second lower metal line.
18. The method of claim 14 , further comprising forming an etch stop liner over the device prior to removing the portion of the least one sacrificial MRAM stack to form the super via trench.
19. The method of claims 14 , further comprising forming a plurality of second sidewall spacers on sidewalls of the MRAM cells, wherein the etch stop is disposed around the plurality of MRAM cells and the super via, and overlaps the first sidewall spacer and the second sidewall spacers.
20. The method of claim 14 , further comprising:
forming a hardmask over the device prior to removing the portion of the sacrificial MRAM stack to form the super via trench; and
patterning the hardmask over the sacrificial MRAM stack.