Granted Patent B2

US 12,259,820 · App. 18/624,301 · Granted Mar 25, 2025

Inventor: Ramkumar Srinivasan (Bangalore, IN)

Assignee: QUALCOMM Incorporated

G06F12/0897G06F12/0891G06F12/126

Abstract

Claims (99)

1. A method for allocating a cache line to a higher-level cache memory in response to an eviction request of a lower-level cache line in a lower-level cache memory, comprising:

determining whether the lower-level cache line is opportunistic;

determining, based on whether the lower-level cache line is opportunistic, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and

in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:

replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating whether the lower-level cache line is opportunistic with the higher-level cache line in the higher-level cache memory.

2. The method of claim 1 , wherein determining whether the higher-level cache line of the plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line comprises:

determining whether the higher-level cache line in the higher-level cache memory is invalid; and

in response to determining the higher-level cache line in the higher-level cache memory is invalid:

replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating whether the lower-level cache line is opportunistic with the higher-level cache line in the higher-level cache memory.

3. The method of claim 1 , further comprising, in response to determining whether the higher-level cache line in the higher-level cache memory is not invalid:

determining whether the higher-level cache line in the higher-level cache memory is opportunistic; and

in response to determining the higher-level cache line is opportunistic:

replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating whether the lower-level cache line is opportunistic with the higher-level cache line in the higher-level cache memory.

4. The method of claim 3 , comprising, in response to determining whether the higher-level cache line in the higher-level cache memory is not opportunistic:

determining whether the lower-level cache line is dirty; and

in response to determining the lower-level cache line is dirty:

writing the lower-level cache line to a system memory.

5. The method of claim 1 , wherein determining whether the higher-level cache line in the higher-level cache memory has less or equal importance than the lower-level cache line further comprises:

determining if a first higher-level cache line has less or equal importance than the lower-level cache line;

determining if a second higher-level cache line has less or equal importance than the lower-level cache line; and

in response to determining the first higher-level cache line has less or equal importance than the lower-level cache line and the second higher-level cache line has less or equal importance than the lower-level cache line:

determining if the first higher-level cache line has less or equal importance than the second higher-level cache line; and

in response to determining that the first higher-level cache line has less or equal importance than the second higher-level cache line:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

6. The method of claim 5 , wherein determining if the first higher-level cache line has less or equal importance than the second higher-level cache line further comprises:

determining if the first higher-level cache line is invalid;

determining if the second higher-level cache line is invalid; and

in response to determining that the first higher-level cache line is invalid and the second higher-level cache line is not invalid:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

7. The method of claim 6 , further comprising, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid:

determining a first priority indicator of the first higher-level cache line and a second priority indicator of the second higher-level cache line; and

in response to determining that the first priority indicator of the first higher-level cache line is less recently used than the second priority indicator of the second higher-level cache line:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

8. The method of claim 6 , comprising, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid:

determining a least recently used (LRU) indicator tracking an order of a plurality of least recently used cache lines, including the first higher-level cache line and the second higher-level cache line; and

in response to determining that the LRU indicator indicates the first higher-level cache line is less recently used than the second higher-level cache line:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

9. A processor-based system for allocating a cache line to a higher-level cache memory in response to an eviction request of a lower-level cache line in a lower-level cache memory, comprising:

means for determining whether the lower-level cache line is opportunistic;

means for determining, based on whether the lower-level cache line is opportunistic, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and

in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:

means for replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

means for associating whether the lower-level cache line is opportunistic with the higher-level cache line in the higher-level cache memory.

10. A processor-based system for allocating a cache line to a higher-level cache memory, comprising:

a lower-level cache memory configured to store data;

the processor-based system configured to, in response to an eviction request of a lower-level cache line in the lower-level cache memory:

determine whether the lower-level cache line is opportunistic;

determine, based on whether the lower-level cache line is opportunistic, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and

in response to determining the higher-level cache line has less or equal importance than the lower-level cache line:

replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate whether the lower-level cache line is opportunistic with the higher-level cache line.

11. The processor-based system of claim 10 , configured to determine whether the higher-level cache line of the plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line by being configured to:

determine whether the higher-level cache line in the higher-level cache memory is invalid; and

in response to determining the higher-level cache line in the higher-level cache memory is invalid:

replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate whether the lower-level cache line is opportunistic with the higher-level cache line in the higher-level cache memory.

12. The processor-based system of claim 11 , further configured, in response to determining the higher-level cache line in the higher-level cache memory is not invalid, to:

determine whether the higher-level cache line in the higher-level cache memory is opportunistic; and

in response to the determining the higher-level cache line is opportunistic:

replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate whether the lower-level cache line is opportunistic with the higher-level cache line in the higher-level cache memory.

13. The processor-based system of claim 12 , further configured, in response to determining the higher-level cache line in the higher-level cache memory is not opportunistic, to:

determine whether the lower-level cache line is dirty; and

in response to determining that the lower-level cache line is dirty:

write the lower-level cache line to a system memory.

14. The processor-based system of claim 10 , wherein the lower-level cache line is opportunistic.

15. The processor-based system of claim 10 , configured to determine whether the higher-level cache line in the higher-level cache memory has less or equal importance than the lower-level cache line by being configured to:

determine if a first higher-level cache line has less or equal importance than the lower-level cache line;

determine if a second higher-level cache line has less or equal importance than the lower-level cache line; and

in response to determining the first higher-level cache line has less or equal importance than the lower-level cache line and the second higher-level cache line has less or equal importance than the lower-level cache line:

determine if the first higher-level cache line has less or equal importance than the second higher-level cache line; and

in response to determining that the first higher-level cache line has less or equal importance than the second higher-level cache line:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

16. The processor-based system of claim 15 , configured to determine if the first higher-level cache line has less or equal importance than the second higher-level cache line by being configured to:

determine if the first higher-level cache line is invalid;

determine if the second higher-level cache line is not invalid; and

in response to determining that the first higher-level cache line is invalid and the second higher-level cache line is not invalid:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

17. The processor-based system of claim 16 , further configured, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, to:

determine a first priority indicator of the first higher-level cache line and a second priority indicator of the second higher-level cache line; and

in response to determining that the first priority indicator of the first higher-level cache line is less recently used than the second priority indicator of the second higher-level cache line:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

18. The processor-based system of claim 16 , further configured, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, to:

determine a least recently used (LRU) indicator tracking an order of a plurality of least recently used cache lines, including the first higher-level cache line and the second higher-level cache line; and

in response to determining that the LRU indicator indicates the first higher-level cache line is less recently used than the second higher-level cache line:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate whether the lower-level cache line is opportunistic with the first higher-level cache line in the higher-level cache memory.

19. The processor-based system of claim 10 integrated into an integrated circuit (IC).

20. The processor-based system of claim 10 integrated into a device selected from a group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.

Assignments (1)

Continuity (3)

References Cited (29)