Granted Patent B2

US 12,261,541 · App. 18/225,512 · Granted Mar 25, 2025

Inventors: Yaming Cao (Shanghai, CN); Wuping Lin (Shanghai, CN); Chunsheng Zhao (Shanghai, CN); Lieyi Fang (Shanghai, CN)

Assignee: On-Bright Electronics (Shanghai) Co., Ltd.

H02M3/33592H02M1/0012H02M1/08

Abstract

Claims (90)

1. A system for synchronous rectification of a power converter, the power converter including a primary winding and a secondary winding, the system comprising:

a first system terminal configured to receive an input voltage; and

a second system terminal configured to output a drive signal to a transistor coupled to the secondary winding;

wherein the system is configured to:

determine whether the input voltage becomes lower than a predetermined voltage threshold; and

if the input voltage becomes lower than the predetermined voltage threshold, determine whether a time when the input voltage becomes lower than the predetermined voltage threshold is during or not during any demagnetization process of the secondary winding.

2. The system of claim 1 is further configured to, if the time when the input voltage becomes lower than the predetermined voltage threshold is during a demagnetization process of the secondary winding, allow the drive signal to turn on the transistor.

3. The system of claim 2 is further configured to, if the time when the input voltage becomes lower than the predetermined voltage threshold is during the demagnetization process of the secondary winding, generate the drive signal to turn on the transistor if one or more logic conditions are satisfied.

4. The system of claim 1 , and further comprising:

a voltage detector configured to process information associated with the input voltage and generate a detection signal based on at least the information associated with the input voltage; and

a driver configured to process information associated with the detection signal and generate the drive signal based on at least the information associated with the detection signal.

5. The system of claim 4 wherein the voltage detector is further configured to:

determine whether a downward slope of the input voltage is larger than a predetermined slope threshold; and

determine whether the input voltage becomes smaller than the predetermined voltage threshold.

6. The system of claim 5 wherein the voltage detector is further configured to, if the downward slope of the input voltage is larger than the predetermined slope threshold and the input voltage becomes smaller than the predetermined voltage threshold, determine that the time when the input voltage becomes lower than the predetermined voltage threshold is during a demagnetization process of the secondary winding.

7. The system of claim 5 wherein the voltage detector is further configured to, if the downward slope of the input voltage is smaller than the predetermined slope threshold and the input voltage becomes smaller than the predetermined voltage threshold, determine that the time when the input voltage becomes lower than the predetermined voltage threshold is not during any demagnetization process of the secondary winding.

8. The system of claim 4 wherein the voltage detector includes:

a first comparator configured to receive a first comparator threshold and a first comparator voltage directly proportional to the input voltage and generate a first comparison signal based at least in part on the first comparator threshold and the first comparator voltage;

a timer configured to receive the first comparison signal and generate a timer signal based at least in part on the first comparison signal and a predetermined duration of time;

a second comparator configured to receive the predetermined voltage threshold and a second comparator voltage directly proportional to the input voltage and generate a second comparison signal based at least in part on the predetermined voltage threshold and the second comparator voltage; and

a flip-flop configured to receive the timer signal and the second comparison signal and generate the detection signal based at least in part on the timer signal and the second comparison signal;

wherein the first comparator threshold is higher than the predetermined voltage threshold.

9. The system of claim 8 wherein the first comparator voltage and the second comparator voltage are the same.

10. The system of claim 9 wherein:

the first comparator voltage is equal to the input voltage; and

the second comparator voltage is equal to the input voltage.

11. The system of claim 8 wherein:

the timer is further configured to, if the first comparison signal indicates that the first comparator voltage becomes smaller than the first comparator threshold at a first time, generate the timer signal at a first logic level from the first time until a second time;

wherein a time duration from the first time to the second time is equal to the predetermined duration of time.

12. The system of claim 11 wherein the timer is further configured to, if the first comparison signal indicates that the first comparator voltage becomes smaller than the first comparator threshold at the first time, change the timer signal from the first logic level to a second logic level at the second time.

13. The system of claim 12 wherein the flip-flop is further configured to, if the second comparison signal indicates that the second comparator voltage becomes smaller than the predetermined voltage threshold at a third time, generate the detection signal to be the same as the timer signal at the third time.

14. The system of claim 13 wherein the flip-flop is further configured to, if the third time is after the first time but before the second time, generate the detection signal to be the first logic level.

15. The system of claim 14 wherein the flip-flop is further configured to, if the third time is after the second time, generate the detection signal to be the second logic level.

16. The system of claim 15 is further configured to:

if the detection signal is at the first logic level, determine that the time when the input voltage becomes lower than the predetermined voltage threshold is during a demagnetization process of the secondary winding; and

if the detection signal is at the second logic level, determine that the time when the input voltage becomes lower than the predetermined voltage threshold is not during any demagnetization process of the secondary winding.

17. The system of claim 4 wherein the voltage detector includes:

a voltage divider configured to receive the input voltage and generate one or more divider voltages;

wherein:

a first comparator voltage is one voltage of the one or more divider voltages; and

a second comparator voltage is one voltage of the one or more divider voltages.

18. The system of claim 4 wherein the voltage detector includes:

a threshold voltage generator configured to receive a generator voltage indicating a magnitude of an output voltage of the power converter and generate the first comparator threshold based at least in part on the generator voltage;

wherein:

a first comparator threshold increases with an increasing generator voltage; and

a first comparator threshold decreases with a decreasing generator voltage.

19. The system of claim 18 wherein the generator voltage is the output voltage of the power converter.

20. The system of claim 4 wherein the voltage detector includes:

a peak detector configured to receive a first detector voltage indicating a magnitude of the first comparator voltage, detect a peak magnitude of the first detector voltage, and generate a second detector voltage representing the detected peak magnitude;

wherein a first comparator is configured to receive the second detector voltage as the first comparator threshold.

21. The system of claim 20 wherein the first detector voltage is the same as the first comparator voltage.

22. The system of claim 21 wherein the first detector voltage is directly proportional to the first comparator voltage.

23. The system of claim 4 wherein the voltage detector includes:

a first comparator configured to receive a first comparator threshold and a first comparator voltage directly proportional to the input voltage and generate a first comparison signal based at least in part on the first comparator threshold and the first comparator voltage;

a timer configured to receive the first comparison signal and generate a timer signal based at least in part on the first comparison signal and a predetermined duration of time;

a second comparator configured to receive a second comparator threshold and a second comparator voltage directly proportional to the input voltage and generate a second comparison signal based at least in part on the second comparator threshold and the second comparator voltage;

a flip-flop configured to receive the timer signal and the second comparison signal and generate a flip-flop signal based at least in part on the timer signal and the second comparison signal;

a third comparator configured to receive the predetermined voltage threshold and a third comparator voltage directly proportional to the input voltage and generate a third comparison signal based at least in part on the predetermined voltage threshold and the third comparator voltage; and

a signal generator configured to receive the flip-flop signal and the third comparison signal and generate the detection signal based at least in part on the flip-flop signal and the third comparison signal;

wherein:

the first comparator threshold is higher than the second comparator threshold;

the predetermined voltage threshold is different from the first comparator threshold; and

the predetermined voltage threshold is different from the second comparator threshold.

24. The system of claim 23 wherein:

the timer is further configured to, if the first comparison signal indicates that the first comparator voltage becomes smaller than the first comparator threshold at a first time, generate the timer signal at a first logic level from the first time until a second time;

wherein a time duration from the first time to the second time is equal to the predetermined duration of time.

25. The system of claim 24 wherein the timer is further configured to, if the first comparison signal indicates that the first comparator voltage becomes smaller than the first comparator threshold at the first time, change the timer signal from the first logic level to a second logic level at the second time.

26. The system of claim 25 wherein the flip-flop is further configured to, if the second comparison signal indicates that the second comparator voltage becomes smaller than the second comparator threshold at a third time, generate the flip-flop signal to be the same as the timer signal at the third time.

27. The system of claim 26 wherein the flip-flop is further configured to, if the third time is after the first time but before the second time, generate the flip-flop signal to be the first logic level.

28. The system of claim 27 wherein the flip-flop is further configured to, if the third time is after the second time, generate the flip-flop signal to be the second logic level.

29. The system of claim 28 wherein the signal generator is further configured to, if the flip-flop signal is at the first logic level and the third comparison signal indicates that the third comparator voltage is smaller than the predetermined voltage threshold, generate the detection signal indicating that the time when the input voltage becomes lower than the predetermined voltage threshold is during a demagnetization process of the secondary winding.

30. A method for synchronous rectification of a power converter, the power converter including a primary winding and a secondary winding, the method comprising:

receiving an input voltage;

processing information associated with the input voltage;

generating a drive signal based on at least information associated with the input voltage; and

outputting the drive signal to a transistor coupled to the secondary winding;

wherein the processing information associated with the input voltage includes:

determining whether the input voltage becomes lower than a predetermined voltage threshold; and

if the input voltage becomes lower than the predetermined voltage threshold, determining whether a time when the input voltage becomes lower than the predetermined voltage threshold is during or not during any demagnetization process of the secondary winding.

31. The method of claim 30 wherein the generating the drive signal based on at least information associated with the input voltage includes:

if the time when the input voltage becomes lower than the predetermined voltage threshold is during a demagnetization process of the secondary winding, allowing the drive signal to turn on the transistor.

32. The method of claim 31 wherein the generating the drive signal based on at least information associated with the input voltage further includes:

if the time when the input voltage becomes lower than the predetermined voltage threshold is during a demagnetization process of the secondary winding, generating the drive signal to turn on the transistor if one or more logic conditions are satisfied.

33. The method of claim 30 wherein the processing information associated with the input voltage further includes:

determining whether a downward slope of the input voltage is larger than a predetermined slope threshold; and

determining whether the input voltage becomes smaller than the predetermined voltage threshold.

34. The method of claim 33 wherein the processing information associated with the input voltage further includes:

if the downward slope of the input voltage is larger than the predetermined slope threshold and the input voltage becomes smaller than the predetermined voltage threshold, determining that the time when the input voltage becomes lower than the predetermined voltage threshold is during a demagnetization process of the secondary winding.

35. The method of claim 34 wherein the processing information associated with the input voltage further includes:

if the downward slope of the input voltage is smaller than the predetermined slope threshold and the input voltage becomes smaller than the predetermined voltage threshold, determining that the time when the input voltage becomes lower than the predetermined voltage threshold is not during any demagnetization process of the secondary winding.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (265)

Cited By (2)

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