Adaptive integrated programmable device platform
A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.
1. A System-on-Chip, comprising:
a data processing engine array comprising a plurality of data processing engines organized in a grid with each data processing engine including a stream switch, a core, and a memory module;
wherein each data processing engine is capable of conveying data to a different data processing engine via a first data path using the stream switch and via at least a second data path independent of the first data path in which the core accesses a memory module of an adjacent data processing engine via a memory interface, wherein the second data path circumvents the stream switch;
wherein the plurality of data processing engines are partitioned into at least a first partition and a second partition;
wherein the first partition includes one or more first data processing engines of the plurality of data processing engines;
wherein the second partition includes one or more second data processing engines of the plurality of data processing engines; and
wherein each partition is configured to implement an application that executes independently of the other partition.
2. The System-on-Chip of claim 1 , wherein both the first partition and the second partition are used by a same user.
3. The System-on-Chip of claim 1 , wherein the data processing engine array is configured for concurrent multi-tenant operation, and wherein the first partition corresponds to a first user and the second partition corresponds to a second user.
4. The System-on-Chip of claim 3 , wherein the first user is only permitted to access configuration registers of the first partition and the second user is only permitted to access configuration registers of the second partition.
5. The System-on-Chip of claim 3 , wherein during operation of the System-on-Chip, the first user is removed from the first partition, the first partition is allocated to a third user, and the first partition implements a further application corresponding to the third user.
6. The System-on-Chip of claim 1 , wherein the first partition executes a first application and the second partition executes a second and different application concurrently with the first application.
7. The System-on-Chip of claim 1 , wherein each partition implements error handling independently of the other partition.
8. The System-on-Chip of claim 1 , further comprising:
a processor system coupled to the data processing engine array.
9. The System-on-Chip of claim 1 , further comprising:
a network-on-chip coupled to the data processing engine array.
10. The System-on-Chip of claim 1 , further comprising:
a programmable logic coupled to the data processing engine array.
11. A System-on-Chip, comprising:
a data processing engine array comprising a plurality of data processing engines organized in a grid, wherein the plurality of data processing engines are partitioned into at least a first partition including one or more first data processing engines of the plurality of data processing engines and a second partition including one or more second data processing engines of the plurality of data processing engines;
wherein each partition is configured to implement an application that executes independently of the other partition; and
a network-on-chip coupled to the data processing engine array, wherein the network-on-chip is programmable to establish user specified data paths communicatively linking the first partition and the second partition with one or more other systems of the System-on-Chip.
12. The System-on-Chip of claim 11 , wherein both the first partition and the second partition are used by a same user.
13. The System-on-Chip of claim 11 , wherein the data processing engine array is configured for concurrent multi-tenant operation, and wherein the first partition corresponds to a first user and the second partition corresponds to a second user.
14. The System-on-Chip of claim 13 , wherein the first user is only permitted to access configuration registers of the first partition and the second user is only permitted to access configuration registers of the second partition.
15. The System-on-Chip of claim 13 , wherein during operation of the System-on-Chip, the first user is removed from the first partition, the first partition is allocated to a third user, and the first partition implements a further application corresponding to the third user.
16. The System-on-Chip of claim 11 , wherein the first partition executes a first application and the second partition executes a second and different application concurrently with the first application.
17. The System-on-Chip of claim 11 , wherein each partition implements error handling independently of the other partition.
18. The System-on-Chip of claim 11 , wherein the one or more other systems include a processor system.
19. The System-on-Chip of claim 11 , wherein the one or more other systems include a programmable logic.