Apparatus with circuit-locating mechanism
An apparatus includes a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels for representing physical locations of the circuit components within the apparatus.
1. An apparatus, comprising:
a substrate;
circuit components disposed on the substrate;
a planar mesh over the circuit components and including one or more section labels configured to provide locational reference to the circuit components; and
a protective layer over the planar mesh.
2. The apparatus of claim 1 , wherein the planar mesh is a metal mesh and the one or more section labels include filler material patterned into the planar mesh.
3. The apparatus of claim 2 , wherein the planar mesh is electrically conductive and comprises a top metal layer.
4. The apparatus of claim 2 , wherein the filler material is a dummy filler.
5. The apparatus of claim 2 , wherein the top metal layer is configured to connect to a supply voltage or a ground connection.
6. The apparatus of claim 1 , wherein each of the section labels (1) correspond to a macro-cell that includes a region in the planar mesh, and (2) include a number, a letter, or a combination thereof for identifying the unique region.
7. The apparatus of claim 6 , wherein:
the planar mesh includes slots; and
the one or more section labels correspond to the filler material occupying a subset of the slots to provide the unique set of numbers, letters, symbols, or the combination thereof.
8. The apparatus of claim 1 , wherein:
the planar mesh includes slots that correspond to label pixels; and
the one or more section labels comprise filler material occupying corresponding label pixels, wherein each of the occupied label pixels is configured to provide a locational reference for a corresponding portion of the circuit components.
9. The apparatus of claim 1 , wherein:
the protective layer includes a top passivation layer; and
the one or more section labels are detectable through the top passivation layer.
10. The apparatus of claim 9 , wherein:
the top passivation layer includes a first material; and
the one or more section labels include a second material having at least one physical characteristic different than the first material.
11. A method of manufacturing an apparatus, the method comprising:
providing a substrate;
forming circuit components on the substrate;
forming one or more section labels over the circuit, wherein the one or more section labels are (1) included on a planar mesh that is over the circuit components and (2) located relative to the circuit components for providing locational reference to the circuit components; and
forming a protective layer over the planar mesh.
12. The method of claim 11 , wherein forming the one or more section labels includes:
attaching the planar mesh structure over the circuit components; and
patterning filler material into the planar mesh to form the one or more section labels.
13. The method of claim 12 , wherein:
the planar mesh includes slots that correspond label pixels; and
the one or more section labels comprise the filler material occupying corresponding pixels, wherein each of the occupied pixels is configured to provide a locational reference for a corresponding portion of the circuit components.
14. The method of claim 12 , wherein the one or more section labels include a unique set of pixelated numbers, letters, symbols, or the combination thereof.
15. The method of claim 12 , wherein the filler material is a dummy filler and includes material different from the protective layer, wherein the dummy filler is detectable through the protective layer.
16. The method of claim 11 , wherein the planar mesh is a top metal layer.
17. The method of claim 16 , further comprising:
connecting the metallic layer to a voltage source or an electrical ground.
18. A semiconductor device, comprising:
a substrate;
circuitry on the substrate, wherein the circuitry is along at least one lateral plane;
a planar mesh over the circuitry, wherein the planar mesh includes filler material forming a letter, a number, a symbol, or a combination thereof configured to provide locational reference to the circuitry; and
an encapsulant over the top metal layer, the circuit layer, and the substrate.
19. The semiconductor device of claim 18 , wherein:
the planar mesh is a top metal layer that includes slots that correspond to pixels; and
the letter, the number, the symbol, or a combination thereof are pixelated and comprise the filler material occupying corresponding instances of the pixels.
20. The semiconductor device of claim 18 , wherein:
the filler includes material different from the encapsulant and detectable through the encapsulant.