Reliable electronic fuse based storage using error correction coding
An apparatus for reliable fuse-based storage in an Integrated Circuit (IC) includes a plurality of electronic fuses and processing logic. The electronic fuses store (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits. The processing logic receives a read command for reading given data bits from the electronic fuses, based on the read command retrieves access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits, using the access information reads the given data bits and the given parity bits from the given electronic fuses, applies the ECC scheme to the given data bits and the given parity bits, using the ECC module to generate corrected data bits, and outputs the corrected data bits.
1. An apparatus for reliable fuse-based storage in an Integrated Circuit (IC), the apparatus comprising:
a plurality of electronic fuses configured to store (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits;
an ECC module, configured to apply the ECC scheme to the data bits and corresponding parity bits for correcting errors in the data bits; and
processing logic configured to:
receive, from a Built-In Self-Repair (BISR) controller, a read command for reading given data bits from the electronic fuses; and
respond to the read command while rendering the BISR controller unaware of the ECC scheme, by:
based on the read command, retrieving the access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits;
reading, using the access information, the given data bits and the given parity bits from the given electronic fuses;
applying the ECC scheme to the given data bits and the given parity bits, using the ECC module, to generate corrected data bits; and
outputting the corrected data bits to the BISR controller.
2. The apparatus for reliable fuse-based storage according to claim 1 , wherein the processing logic is configured to retrieve the access information by reading a start location and an end location of a range of the electronic fuses among the plurality of electronic fuses.
3. The apparatus for reliable fuse-based storage according to claim 1 , wherein, by rendering the BISR controller unaware of the ECC scheme, the processing logic is configured to provide the BISR controller with reliable indirect access to data stored in the plurality of electronic fuses.
4. The apparatus for reliable fuse-based storage according to claim 3 , wherein the BISR controller is coupled to the apparatus via an interface supporting generic signals that are applicable by the BISR controller for direct access to electronic fuses other than the electronic fuses in the plurality of electronic fuses.
5. The apparatus for reliable fuse-based storage according to claim 1 , wherein the processing logic comprises a rewritable memory, which is configured to store temporary data bits to be written to the electronic fuses or read from the electronic fuses, and wherein the processing logic is configured to calculate temporary parity bits corresponding to the temporary data bits in the rewritable memory using the ECC module.
6. The apparatus for reliable fuse-based storage according to claim 5 , wherein a number of the temporary data bits is smaller than an input size required by the ECC scheme, and wherein the processing logic is configured to pad the temporary data bits with one or more padding bits to complete the input size required by the ECC scheme.
7. The apparatus for reliable fuse-based storage according to claim 1 , wherein the processing logic is configured, prior to writing any data to the plurality of electronic fuses, to perform a fuse test for verifying that the electronic fuses being initially unblown, under control of an external device by disabling the ECC module and providing direct access to the electronic fuses.
8. The apparatus for reliable fuse-based storage according to claim 1 , wherein the ECC module supports multiple ECC schemes, and wherein the processing logic is configured to select one of the ECC schemes depending on a number of the given data bits.
9. The apparatus for reliable fuse-based storage according to claim 1 , wherein the processing logic is configured to:
receive a write command specifying input data bits, and an address indicative of first electronic fuses for storing the input data bits;
apply the ECC scheme to the input data bits, using the ECC module, to generate input parity bits corresponding to the input data bits;
determine access information indicative of the first electronic fuses, and of second electronic fuses for storing the input parity bits; and
store (i) the input data bits in the first electronic fuses, (ii) the input parity bits in the second electronic fuses, and (iii) the access information in third electronic fuses.
10. A method for reliable fuse-based storage in an Integrated Circuit (IC), the method comprising:
in an apparatus comprising a plurality of electronic fuses storing (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits;
receiving, from a Built-In Self-Repair (BISR) controller, a read command for reading given data bits from the electronic fuses; and
responding to the read command while rendering the BISR controller unaware of the ECC scheme, by:
based on the read command, retrieving the access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits;
reading, using the access information, the given data bits and the given parity bits from the given electronic fuses;
applying the ECC scheme to the given data bits and the given parity bits to generate corrected data bits; and
outputting the corrected data bits to the BISR controller.
11. The method according to claim 10 , wherein retrieving the access information comprises reading a start location and an end location of a range of the electronic fuses among the plurality of electronic fuses.
12. The method according to claim 10 , wherein rendering the BISR controller unaware of the ECC scheme comprises providing the BISR controller with reliable indirect access to data stored in the plurality of electronic fuses.
13. The method according to claim 12 , wherein the BISR controller is coupled to the apparatus via an interface supporting generic signals that are applicable by the BISR for direct access to electronic fuses other than the electronic fuses in the plurality of electronic fuses.
14. The method according to claim 10 , wherein the apparatus comprises a rewritable memory that stores temporary data bits to be written to the electronic fuses or read from the electronic fuses, comprising calculating temporary parity bits corresponding to the temporary data bits in the rewritable memory using the ECC module.
15. The method according to claim 14 , wherein a number of the temporary data bits is smaller than an input size required by the ECC scheme, and comprising padding the temporary data bits with one or more padding bits to complete the input size required by the ECC scheme.
16. The method according to claim 10 , further comprising, prior to writing any data to the plurality of electronic fuses, performing a fuse test for verifying that the electronic fuses being initially unblown, under control of an external device by disabling the ECC module and providing direct access to the electronic fuses.
17. The method according to claim 10 , wherein the apparatus supports multiple ECC schemes, and comprising selecting one of the ECC schemes depending on a number of the given data bits.
18. The method according to claim 10 , and comprising:
receiving a write command specifying input data bits, and an address indicative of first electronic fuses for storing the input data bits;
applying the ECC scheme to the input data bits to generate input parity bits corresponding to the input data bits;
determining access information indicative of the first electronic fuses, and of second electronic fuses for storing the input parity bits; and
storing (i) the input data bits in the first electronic fuses, (ii) the input parity bits in the second electronic fuses, and (iii) the access information in third electronic fuses.