IP Library › Granted Patent US 12,266,622
Granted Patent B2
US 12,266,622 · App. 17/840,081 · Granted Apr 1, 2025

Method of manufacturing semiconductor structure having hybrid bonding pad

Inventor: Yi-Jen Lo (New Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L24/06H01L24/08H01L24/80H01L2224/06517H01L2224/08145H01L2224/80895H01L2224/80896
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Quick Facts
Patent No.
US 12,266,622
App. No.
17/840,081
Granted
Apr 1, 2025
Kind
B2
Abstract

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a first semiconductor substrate. The method also includes forming a first conductive pad over the first semiconductor substrate. The method further includes forming a first hybrid bonding pad on the first conductive pad, wherein the first hybrid bonding pad includes nano-twins copper, and a thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad.

Claims (23)

1. A method of manufacturing a semiconductor structure, comprising:

providing a first semiconductor substrate;

forming a first conductive pad over the first semiconductor substrate;

forming a first hybrid bonding pad on the first conductive pad, wherein the first hybrid bonding pad comprises nano-twins copper, and a thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad;

providing a second semiconductor substrate;

forming a second conductive pad over the second semiconductor substrate; and

forming a second hybrid bonding pad on the second conductive pad, wherein the second hybrid bonding pad comprises nano-twins copper.

2. The method of claim 1 , wherein a hybrid bonding surface of the first hybrid bonding pad comprises a [111] crystal plane.

3. The method of claim 1 , further comprising:

forming a first dielectric layer over the first semiconductor substrate; and

forming a first trench in the first dielectric layer.

4. The method of claim 3 , wherein forming the first conductive pad comprises:

depositing a conductive material in the first trench.

5. The method of claim 3 , further comprising:

forming a second dielectric layer on the first dielectric layer and the first conductive pad; and

forming a second trench penetrating the second dielectric layer to expose the first conductive pad, wherein a depth of the second trench is less than a depth of the first trench.

6. The method of claim 5 , wherein forming the first hybrid bonding pad comprises:

forming a nano-twins copper layer in the second trench, wherein at least 80% of a surface area of a hybrid bonding surface of the first hybrid bonding pad is a [111] crystal plane.

7. The method of claim 1 , further comprising:

forming an interconnection structure on the first semiconductor substrate, wherein the first conductive pad is formed on the interconnection structure.

8. The method of claim 1 , further comprising:

connecting the first semiconductor substrate to the second semiconductor substrate by bonding the first hybrid bonding pad to the second hybrid bonding pad.

9. The method of claim 1 , wherein a hybrid bonding surface of the second hybrid bonding pad comprises a [111] crystal plane, and a thickness of the second hybrid bonding pad is less than a thickness of the second conductive pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2022
From: LO, YI-JEN
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 061453/0432 →
Continuity (1)
Related Publication 20230402413A1 · Dec 14, 2023
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Cited By (1)
US 12,733,560