Package process and package structure
A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.
1. A package structure, comprising:
a first semiconductor device;
a second semiconductor device disposed over the first semiconductor device;
a conductive bump connected to the first semiconductor device and the second semiconductor device;
a first underfill disposed between the first semiconductor device and the second semiconductor device, and covering a lateral surface of the conductive bump;
a second molding compound covering the second semiconductor device and a lateral surface of the first underfill, wherein the second molding compound is spaced apart from the first semiconductor device;
a second underfill disposed under the first semiconductor device, wherein at least a portion of the second underfill is spaced apart from a lateral surface of the first semiconductor device; and
a third molding compound covering a lateral surface of the second semiconductor device and laterally overlapping the second underfill.
2. The package structure of claim 1 , wherein the first underfill covers the first semiconductor device.
3. The package structure of claim 2 , wherein the first underfill contacts the lateral surface of the conductive bump.
4. The package structure of claim 3 , wherein an interface is formed between the second molding compound and the lateral surface of the first underfill, and wherein a surface of the first semiconductor device is co-level with a bottom surface of the second molding compound and a bottom surface of the first underfill.
5. The package structure of claim 1 , wherein the third molding compound contacts the second underfill.
6. The package structure of claim 1 , wherein the third molding compound covers the second molding compound.
7. The package structure of claim 6 , wherein a top surface of the third molding compound exposes a top surface of the second semiconductor device, wherein the third molding compound includes an inner lateral surface facing the second semiconductor device and an outer lateral surface opposite to the inner lateral surface, and wherein a width of the exposed top surface of the second semiconductor device is greater than a distance between the inner lateral surface and the outer lateral surface in a cross-sectional view.