Leakage reduction in gate-all-around devices
View Patent ↗A semiconductor device includes a substrate, a p-type well over the substrate and having a p-type anti-punch-through (APT) layer, an n-type source feature and an n-type drain feature over the p-type APT layer, and multiple first channel layers suspended over the p-type APT layer and connecting the n-type source feature to the n-type drain feature. The multiple first channel layers are vertically stacked one over another and are undoped. The semiconductor device further includes a high-k metal gate wrapping around each of the first channel layers, a first source contact disposed over and electrically coupled to the n-type source feature, and a drain contact disposed over and electrically coupled to the n-type drain feature. A bottom surface of the n-type source feature is about 5 nm to about 25 nm below an interface between the high-k metal gate and the p-type APT layer.
1. A semiconductor device, comprising:
a substrate;
a well of a first conductivity-type over the substrate and having an anti-punch-through (APT) layer of the first conductivity-type,
a source feature and a drain feature both of a second conductivity-type over the APT layer, wherein the first conductivity-type is different than the second conductivity-type;
multiple first channel layers suspended over the APT layer and connecting the source feature to the drain feature, wherein the multiple first channel layers are vertically stacked one over another and are undoped;
a high-k metal gate wrapping around each of the first channel layers and having an interface with the APT layer, wherein a bottom surface of the source feature is below the interface;
a first source contact disposed over and electrically coupled to the source feature;
a drain contact disposed over and electrically coupled to the drain feature;
a first source via landed on the first source contact; and
a first strap via landed on a first strap contact, wherein, during a non-active mode of the semiconductor device, the first source via is configured to be coupled to ground and the first strap via is configured to be coupled to a first voltage that is lower than ground.
2. The semiconductor device of claim 1 , wherein the first conductivity-type is p-type, and the second conductivity-type is n-type, the semiconductor device further comprising:
a p-type strap epitaxial feature disposed over the p-type well; and
the first strap contact disposed over and electrically coupled to the p-type strap epitaxial feature.
3. The semiconductor device of claim 2 , wherein the first voltage that is lower than ground by about 0.1V to about 0.6V.
4. The semiconductor device of claim 2 , further comprising:
inner dielectric spacers disposed between the high-k metal gate and the n-type source feature, and the n-type drain feature respectively; and
top dielectric spacers disposed over sidewalls of the high-k metal gate and over a topmost one of the first channel layers.
5. The semiconductor device of claim 2 , further comprising:
an n-type well over the substrate and having an n-type anti-punch-through (APT) layer;
a p-type source feature and a p-type drain feature over the n-type APT layer;
multiple second channel layers suspended over the n-type APT layer and connecting the p-type source feature to the p-type drain feature, wherein the multiple second channel layers are vertically stacked one over another and are undoped, wherein the high-k metal gate also wraps around each of the second channel layers, wherein a bottom surface of the p-type source feature is about 5 nm to about 25 nm below an interface between the high-k metal gate and the n-type APT layer; and
a second source contact disposed over and electrically coupled to the p-type source feature, wherein the drain contact is also disposed over and electrically coupled to the p-type drain feature.
6. The semiconductor device of claim 5 , further comprising:
an n-type strap epitaxial feature disposed over the n-type well;
a second source via landed on the second source contact; and
a second strap contact disposed over and electrically coupled to the n-type strap epitaxial feature.
7. The semiconductor device of claim 6 , further comprising:
a second strap via landed on the second strap contact, wherein, during the non-active mode of the semiconductor device, the second source via is configured to be coupled to a positive supply voltage, and the second strap via is configured to be coupled to a second voltage that is higher than the positive supply voltage.
8. The semiconductor device of claim 7 , wherein the second voltage is higher than the positive supply voltage by about 0.1V to about 0.6V.
9. The semiconductor device of claim 1 , wherein the first conductivity-type is p-type, and the second conductivity-type is n-type, and wherein a ratio of a p-type dopant concentration in the p-type APT layer to another p-type dopant concentration in the p-type well is in a range of about 2 to about 100.
10. A device, comprising:
a semiconductor substrate;
a well of a first conductivity-type over the semiconductor substrate;
an anti-punch-through (APT) layer of the first conductivity-type;
a first conductivity-type strap epitaxial feature is disposed over the well;
a source feature and a drain feature over the APT layer having a second conductivity-type opposite of the first conductivity-type;
an isolation feature over the semiconductor substrate, wherein the APT layer contacts an upper portion of a sidewall of the isolation feature and the well contacts a lower portion of the sidewall of the isolation feature;
multiple first channel layers suspended over the APT layer and connecting the source feature to the drain feature, wherein the multiple first channel layers are vertically stacked one over another;
a high-k metal gate wrapping around each of the first channel layers, wherein a bottom surface of the source feature is below an interface between the high-k metal gate and the APT layer;
a first source contact disposed over and electrically coupled to the source feature; and
a drain contact disposed over and electrically coupled to the drain feature.
11. The device of claim 10 , wherein
the APT layer contacts the well with an interface at a level distanced from a top surface and a bottom surface of the isolation feature; and
the first conductivity-type is p-type, and the second conductivity-type is n-type.
12. The device of claim 10 , wherein the multiple first channel layers are free from a first conductivity-type dopant.
13. The device of claim 10 , further comprising:
a first strap contact disposed over and electrically coupled to the first conductivity-type strap epitaxial feature;
a first source via landed on the first source contact; and
a first strap via landed on the first strap contact, wherein, during a non-active mode of the device, the first source via is configured to be coupled to ground and the first strap via is configured to be coupled to a first voltage that is lower than ground.
14. The device of claim 13 , wherein the first voltage that is lower than ground by about 0.1V to about 0.6V.
15. The device of claim 10 , further comprising:
a second conductivity-type strap epitaxial feature disposed over a second conductivity-type well;
a second source via landed on a second source contact; and
a second strap contact disposed over and electrically coupled to the second conductivity-type strap epitaxial feature.
16. The device of claim 15 , further comprising:
a second strap via landed on the second strap contact, wherein, during a non-active mode of the device, the second source via is configured to be coupled to a positive supply voltage, and the second strap via is configured to be coupled to a second voltage that is higher than the positive supply voltage.
17. A semiconductor device, comprising:
a substrate;
a well of a first conductivity-type over the substrate;
an anti-punch-through (APT) layer of the first conductivity-type;
a first conductivity-type strap epitaxial feature is disposed over the well;
a source feature and a drain feature both of a second conductivity-type over the APT layer;
multiple first channel layers suspended over the APT layer which connects the source feature to the drain feature, wherein the multiple first channel layers are vertically stacked one over another;
a high-k metal gate wrapping around each of the first channel layers and having an interface with the APT layer, wherein a bottom surface of the source feature extends below the interface, and the high-k metal gate includes a work function metal layer and a metal fill layer;
a first source contact disposed over and electrically coupled to the source feature; and
a drain contact disposed over and electrically coupled to the drain feature,
wherein the metal fill layer is disposed over a top surface of the work function metal layer and extends into trenches of the work function metal layer at both sides of the multiple first channel layers to a level below a bottommost one of the multiple first channel layers.
18. The semiconductor device of claim 17 , wherein the first conductivity-type is p-type, and the second conductivity-type is n-type, the semiconductor device further comprising:
the work function metal layer having a first portion, a second portion and a third portion, wherein a first one of the trenches is defined between the first and the second portion, and wherein a second one of the trenches is defined between the second and the third portion; and
the metal fill layer includes a top portion continuously extends from the first portion to the third portion of the work function metal layer, wherein the top portion directly contacts top surfaces of the first, second and third portions.
19. The semiconductor device of claim 18 , further comprising:
a first strap via landed on a first strap contact;
a first source via landed on the first source contact; and
the first strap contact disposed over and electrically coupled to the first conductivity-type strap epitaxial feature,
wherein, during a non-active mode of the semiconductor device, the first source via is configured to be coupled to ground and the first strap via is configured to be coupled to a first voltage that is lower than ground.
20. The semiconductor device of claim 19 , wherein the first voltage that is lower than ground by about 0.1V to about 0.6V.