Field-effect transistor crescent-shaped dielectric isolation
A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.
1 . A semiconductor structure, wherein the semiconductor structure comprises:
a transistor comprising nanosheets and an epi, wherein the epi is directly connected to the nanosheets;
a substrate, wherein the epi is directly connected to the substrate; and
an isolation layer directly connected to the epi and the substrate.
2 . The semiconductor structure of claim 1 , wherein the isolation layer is at a bottom area of a well in the substrate.
3 . The semiconductor structure of claim 2 , wherein the epi is connected to the substrate at sidewalls of the well.
4 . The semiconductor structure of claim 1 , wherein the isolation layer is a crescent shape.
5 . The semiconductor structure of claim 1 , wherein the isolation layer comprises at least one of SiN, SiBCN, SiOCN, SiC, and SiOC.
6 . The semiconductor structure of claim 1 , wherein a first portion of the epi directly connected to the isolation layer is greater than a second portion of the epi directly connected to the substrate.
7 . The semiconductor structure of claim 1 , wherein the transistor is a bottom transistor in a stacked transistor structure.
8 . The semiconductor structure of claim 1 , wherein the transistor is a nanosheet FET.
9 . A system, wherein the system comprises:
a semiconductor structure, wherein the semiconductor structure comprises:
a first transistor comprising nanosheets and a first epi, wherein the first epi is directly connected to the nanosheets;
a second transistor comprising a second epi;
a substrate, wherein the first epi is directly connected to the substrate; and
an isolation layer directly connected to the first epi and the substrate.
10 . The system of claim 9 , wherein the isolation layer is at a bottom area of a well in the substrate.
11 . The system of claim 10 , wherein the first epi is connected to the substrate at sidewalls of the well.
12 . The system of claim 9 , wherein the isolation layer is a crescent shape.
13 . The system of claim 9 , wherein the isolation layer comprises at least one of SiN, SiBCN, SiOCN, SiC, and SiOC.
14 . The system of claim 9 , wherein a first portion of the first epi directly connected to the isolation layer is greater than a second portion of the first epi directly connected to the substrate.
15 . The system of claim 9 , wherein the first transistor is a bottom transistor and the second transistor is a top transistor in a stacked transistor structure.
16 . A method of forming a semiconductor structure, the method comprising:
forming an isolation layer directly connected to a substrate; and
forming a first transistor, wherein forming the first transistor comprises:
growing a first epi, wherein the first epi is directly connected to first transistor nanosheets, the isolation layer and the substrate.
17 . The method of claim 16 , wherein forming the isolation layer comprises:
forming a well within the substrate;
depositing a dielectric in the well; and
shaping the dielectric, resulting in the isolation layer.
18 . The method of claim 17 , wherein forming the well within the substrate comprises:
recessing a portion of the substrate in a curved shape.
19 . The method of claim 17 , wherein the isolation layer is a crescent shape.
20 . The method of claim 19 , wherein shaping the dielectric comprises:
shaping the dielectric into a crescent shape, wherein the shaping comprises:
etching the dielectric such that there is an exposed portion of the well of the substrate that is not in direct contact with the dielectric.