Stacked semiconductor transistor device with different conductivities having nanowire channels
A semiconductor device includes a substrate; a first transistor formed over the substrate; a second transistor formed over the first transistor; a third transistor formed over the substrate; and a fourth transistor formed over the third transistor. The first, second, third, and fourth transistor include first, second, third, and fourth gate electrodes, respectively, and include first, second, third, and fourth source regions and first, second, third, and fourth drain region of first, second, third, and fourth conductivity types, respectively. The first conductivity type is different from the second conductivity type. The third conductivity type is the same as the fourth conductivity type. The first and second gate electrodes are integrated, and the third and fourth gate electrode are integrated.
1. A semiconductor device comprising:
a substrate;
a first semiconductor layer of a first conductivity type formed on the substrate;
a second semiconductor layer of the first conductivity type formed on the substrate;
a first insulation film formed on the first semiconductor layer;
a second insulation film formed on the second semiconductor layer;
a third semiconductor layer of a second conductivity type formed on the first insulation film;
a fourth semiconductor layer of the second conductivity type formed on the second insulation film;
a first nanowire formed between the first semiconductor layer and the second semiconductor layer;
a second nanowire formed between the third semiconductor layer and the fourth semiconductor layer;
a first gate electrode formed between the first semiconductor layer and the second semiconductor layer, and between the third semiconductor layer and the fourth semiconductor layer;
a fifth semiconductor layer of a third conductivity type formed on the substrate;
a sixth semiconductor layer of the third conductivity type formed on the substrate;
a third insulation film formed on the fifth semiconductor layer;
a fourth insulation film formed on the sixth semiconductor layer;
a seventh semiconductor layer of a fourth conductivity type formed on the third insulation film;
a eighth semiconductor layer of the fourth conductivity type formed on the fourth insulation film;
a third nanowire formed between the fifth semiconductor layer and the sixth semiconductor layer;
a fourth nanowire formed between the seventh semiconductor layer and the eighth semiconductor layer;
a second gate electrode formed between the fifth semiconductor layer and the sixth semiconductor layer, and between the seventh semiconductor layer and the eighth semiconductor layer;
a first transistor including the first semiconductor layer, the second semiconductor layer, the first nanowire and the first gate electrode;
a second transistor including the third semiconductor layer, the fourth semiconductor layer, the second nanowire and the first gate electrode,
a third transistor including the fifth semiconductor layer, the sixth semiconductor layer, the third nanowire and the second gate electrode, and
a fourth transistor including the seventh semiconductor layer, the eighth semiconductor layer, the fourth nanowire and second gate electrode,
wherein the first conductivity type is different from the second conductivity type,
the third conductivity type is the same as the fourth conductivity type, and
the first transistor is formed at a same height as the third transistor, and the second transistor is formed at a same height as the fourth transistor.
2. The semiconductor device as claimed in claim 1 , further comprising
a first local wire contacting the first semiconductor layer;
a second local wire contacting the second semiconductor layer;
a third local wire contacting the third semiconductor layer;
a fourth local wire contacting the fourth semiconductor layer;
a fifth local wire contacting the fifth semiconductor layer;
a sixth local wire contacting the sixth semiconductor layer;
a seventh local wire contacting the seventh semiconductor layer; and
an eighth local wire contacting the eighth semiconductor layer,
wherein at least part of the first local wire overlaps at least part of the third local wire in plan view,
at least part of the second local wire overlaps at least part of the fourth local wire in plan view,
at least part of the fifth local wire overlaps at least part of the seventh local wire in plan view, and
at least part of the sixth local wire overlaps at least part of the eighth local wire in plan view.
3. The semiconductor device as claimed in claim 1 , wherein the first conductivity type is of p-type,
wherein the second conductivity type is of n-type, and
wherein the third conductivity type and the fourth conductivity type are of p-type or n-type.
4. The semiconductor device as claimed in claim 1 , wherein output signals of the first transistor and the second transistor are input into the second gate electrode.
5. The semiconductor device as claimed in claim 1 , further comprising:
a plurality of memory cells;
a pair of bit lines connected to the plurality of memory cells;
a column switch circuit connected to the pair of bit lines; and
a column decoder configured to control the column switch circuit,
wherein the column decoder includes the first transistor and the second transistor, and
wherein the column switch circuit includes the third transistor and the fourth transistor.
6. The semiconductor device as claimed in claim 5 , wherein the column decoder includes a plurality of instances of the first transistor and a plurality of instances of the second transistor,
wherein two instances of the first transistor adjacent to each other have one local wire in-between shared with each other, and
wherein two instances of the second transistor adjacent to each other over the two instances of the first transistor adjacent to each other have one local wire in-between shared with each other.