Input/output system applied to network security defense system
A structural encoding unit and an error correction decoding unit are divided. The structure encoding unit is divided into input branch processor and an input proxy processor; and the error correction decoding unit is divided into an output routing processor, an output proxy processor, an adjudication branch processor, an adjudication proxy processor and a voting processor. The input branch processor is used for duplicating and distributing messages, the arbitration branch processor is used for duplicating and distributing data, the voting processor is used for performing voting, and the output routing processor is used for selecting an output result from processing results of the output proxy processor according to a voting result of the voting processor.
1. An input-output system applicable in a network security defense system, the input-output system comprising a structural encoding unit and an error correction decoding unit, wherein:
the structural encoding unit comprises an input branching processor and an input proxy processor, wherein the input branching processor is configured for message replication and distribution, the input branching processor is verified as having no backdoor, and is configured for erasing a memory of generalized disturbance;
the error correction decoding unit comprises an output selecting processor, an output proxy processor, an arbitration branching processor, an arbitration proxy processor and a voting processor, wherein:
the arbitration branching processor is configured to replicate and distribute data,
the voting processor is configured to vote,
the output selecting processor is configured to select, based on a voting result of the voting processor, an output result from processing results of the output proxy processor,
the output selecting processor, the arbitration branching processor and the voting processor are verified as having no backdoor and have the memory erasure function, and
at least the output proxy processor and the arbitration proxy processor are set up with a dynamically heterogeneous redundancy mechanism,
wherein any one of the input branching processor, the output selecting processor, the arbitration branching processor, and the voting processor serves as a target processor,
the target processor is configured with a non-random disturbance memory erasure mechanism,
wherein the target processor is further configured with a redundancy and replacement mechanism, wherein
the redundancy and replacement mechanism enable the target processor to erase a memory of random disturbance; and
the non-random disturbance memory erasure mechanism comprises at least one of program curing, program tamper resistance, data initialization, and data tamper resistance.
2. The system according to claim 1 , wherein
the program curing comprises curing a program running in the target processor to prohibit changing a logic of the program, or curing, for a user, a program running in the target processor, to prohibit the user from changing a logic of the program; and
the program tamper resistance comprises at least one of the following:
comparing a program with a backup thereof, and replacing the program with the backup in response to logic difference between the program and the backup;
restoring, periodically or non-periodically, the program through a preset restoration method in the program;
verifying, in real time or non-real time, the program through a preset verification method; and
correcting, in real time or non-real time, the program based on a preset code for encryption or error correction.
3. The system according to claim 1 , wherein
the data initialization comprises initializing a storage space for data, or cleaning the storage space for the data; and
the data tamper resistance comprises at least one of the following:
comparing the data with a backup thereof, and replacing the data with the backup in response to difference between the data and the backup; and
verifying or correcting the data based on a code for verification, encryption, or error correction preset in the data, and initializing the data in response to a verification result indicating a data change.
4. The system according to claim 1 , wherein
the input branching processor is configured to replicate a received user request message into a plurality of copies, and distribute the plurality of copies of the user request message to the input proxy processor; and
the input proxy processor is set up with the dynamically heterogeneous redundancy mechanism.
5. The system according to claim 1 , wherein
the input proxy processor is configured to receive a user request message, and transmit the user request message to the input branching processor; and
the input branching processor is configured to replicate the user request message into a plurality of copies, and distribute the plurality of copies of the user request message to service executors.
6. An input-output system applicable in a network security defense system, the input-output system comprising a structural encoding unit and an error correction decoding unit, wherein:
the structural encoding unit comprises an input branching processor and an input proxy processor, wherein the input branching processor is configured for message replication and distribution, the input branching processor is verified as having no backdoor, and is configured for erasing a memory of generalized disturbance; and
the error correction decoding unit comprises a voting processor, an output selecting processor and an output proxy processor, wherein
the voting processor is configured to vote,
the output selecting processor is configured to select, based on a voting result of the voting processor, an output result from processing results of the output proxy processor, and
the output selecting processor and the voting processor are verified as having no backdoor and have the memory erasure function,
wherein any one of the input branching processor, the output selecting processor, and the voting processor serves as a target processor,
the target processor is configured with a non-random disturbance memory erasure mechanism,
the target processor is further configured with a redundancy and replacement mechanism, wherein
the redundancy and replacement mechanism enable the target processor to erase a memory of random disturbance; and
the non-random disturbance memory erasure mechanism comprises at least one of program curing, program tamper resistance, data initialization, and data tamper resistance.
7. The system according to claim 6 , wherein
the program curing comprises curing a program running in the target processor to prohibit changing a logic of the program, or curing, for a user, a program running in the target processor, to prohibit the user from changing a logic of the program; and
the program tamper resistance comprises at least one of the following:
comparing a program with a backup thereof, and replacing the program with the backup in response to logic difference between the program and the backup;
restoring, periodically or non-periodically, the program through a preset restoration method in the program;
verifying, in real time or non-real time, the program through a preset verification method; and
correcting, in real time or non-real time, the program based on a preset code for encryption or error correction.
8. The system according to claim 6 , wherein
the data initialization comprises initializing a storage space for data, or cleaning the storage space for the data; and
the data tamper resistance comprises at least one of the following:
comparing the data with a backup thereof, and replacing the data with the backup in response to difference between the data and the backup; and
verifying or correcting the data based on a code for verification, encryption, or error correction preset in the data, and initializing the data in response to a verification result indicating a data change.