Granted Patent B2

US 12,268,020 · App. 17/484,009 · Granted Apr 1, 2025

Inventors: Shogo Mochizuki (Mechanicville, NY); Nicolas Loubet (Guilderland, NY)

Assignee: International Business Machines Corporation

H10D30/797H10D30/031H10D30/6757H10D84/017H10D84/0184H10D84/038H10D84/85H10D30/6735

Abstract

Claims (95)

1. A semiconductor-based structure comprising:

a stack comprising spaced-apart non-sacrificial nanosheets;

a source or drain (S/D) region adjacent to the stack; and

a uniform thickness S/D template layer comprising a first sidewall region, a bottom region, and a second sidewall region:

wherein a lateral thickness of the first sidewall region, a vertical thickness of the bottom region, and a lateral thickness of the second sidewall region are substantially equal; and

wherein the first sidewall region is between and physically separates the spaced-apart non-sacrificial nanosheets from the S/D region.

2. The structure of claim 1 further comprising:

a gate spacer; and

a protective liner on the gate spacer and on a top surface of the S/D region;

wherein the first sidewall region is positioned substantially beneath the protective liner.

3. The structure of claim 1 , wherein:

the bottom region comprises a substantially planar top surface;

the uniform thickness S/D template layer comprises a first type of semiconductor material; and

the S/D region comprises a second type of semiconductor material.

4. The structure of claim 3 , wherein an elemental composition of the first type of semiconductor material is different from an elemental composition of the second type of semiconductor material.

5. The structure of claim 4 , wherein:

the second type of semiconductor material comprises doped silicon germanium; and

a concentration of germanium in the doped silicon germanium is greater than about 25%.

6. The structure of claim 3 , wherein the second type of semiconductor material comprises doped silicon.

7. A semiconductor-based structure comprising:

a high-k metal gate (HKMG) structure comprising an upper HKMG structure and spaced-apart HKMG structures;

a stack comprising spaced-apart non-sacrificial nanosheets and the spaced-part HKMG structures;

wherein the stack further comprises a stack sidewall comprising sidewalls of end regions of the spaced-apart non-sacrificial nanosheets and sidewalls of end regions of the spaced-apart HKMG structures;

a S/D region adjacent to the stack;

a protective liner on a gate spacer and on a top surface of the S/D region; and

a uniform thickness S/D template layer comprising a first sidewall region, a bottom region, and a second sidewall region;

wherein a lateral width dimension of the upper HKMG structure is less than a lateral width dimension of at least one of the spaced-apart HKMG structures;

wherein a lateral thickness of the first sidewall region, a vertical thickness of the bottom region, and a lateral thickness of the second sidewall region are substantially equal; and

wherein the first sidewall region is between and physically separates the spaced-apart non-sacrificial nanosheets from the S/D region.

8. The structure of claim 7 , wherein:

the bottom region comprises a substantially planar top surface;

the uniform thickness S/D template layer comprises a first type of semiconductor material; and

the S/D region comprises a second type of semiconductor material.

9. The structure of claim 8 , wherein an elemental composition of the first type of semiconductor material is different from an elemental composition of the second type of semiconductor material.

10. The structure of claim 8 , wherein the second type of semiconductor material comprises doped silicon germanium.

11. The structure of claim 10 , wherein a concentration of germanium in the doped silicon germanium is greater than about 25%.

12. The structure of claim 8 , wherein the second type of semiconductor material comprises doped silicon.

13. A semiconductor-based structure comprising:

a first semiconductor device formed in a first region of a substrate; and

a second semiconductor device formed in a second region of the substrate;

wherein the first semiconductor device comprises:

a first stack comprising first spaced-apart non-sacrificial nanosheets;

a first source or drain (S/D) region adjacent to the first stack;

a uniform thickness S/D template layer comprising a first sidewall region, a bottom region, and a second sidewall region; and

a protective liner on a gate spacer and on a top surface of the first S/D region;

wherein a lateral thickness of the first sidewall region, a vertical thickness of the bottom region, and a lateral thickness of the second sidewall region are substantially equal; and

wherein the first sidewall region is between and physically separates the first spaced-apart non-sacrificial nanosheets from the first S/D region;

wherein the second semiconductor device comprises:

a second stack comprising second spaced-apart non-sacrificial nanosheets, spaced-apart inner spacers, and spaced-apart high-k metal gate (HKMG) structures; and

a second S/D region adjacent the second stack; and

wherein the second S/D region is physically attached directly to ends of the second spaced-apart non-sacrificial nanosheets.

14. The structure of claim 13 , wherein:

the bottom region comprises a substantially planar top surface;

the uniform thickness S/D template layer comprises a first type of semiconductor material;

the first S/D region comprises a second type of semiconductor material; and

the second S/D region comprises a third type of semiconductor material.

15. The structure of claim 14 , wherein an elemental composition of the first type of semiconductor material, an elemental composition of the second type of semiconductor material, and an elemental composition of the third type of semiconductor material are not the same.

16. The structure of claim 14 , wherein:

the second type of semiconductor material comprises doped silicon germanium; and

the third type of semiconductor material comprises doped silicon.

17. The structure of claim 16 , wherein a concentration of germanium in the doped silicon germanium is greater than about 25%.

18. The structure of claim 14 , wherein:

the second type of semiconductor material comprises doped silicon; and

the third type of semiconductor material comprises doped silicon germanium.

19. A method of forming a semiconductor-based structure, the method comprising forming a first semiconductor device in a first region of a substrate, wherein forming the first semiconductor device comprises:

forming a first stack comprising first spaced-apart non-sacrificial nanosheets;

forming a first source or drain (S/D) region adjacent to the first stack;

forming a protective liner on a gate spacer and on a top surface of the first S/D region; and

forming a uniform thickness S/D template layer comprising a first sidewall region, a bottom region, and a second sidewall region;

wherein a lateral thickness of the first sidewall region, a vertical thickness of the bottom region, and a lateral thickness of the second sidewall region are substantially equal; and

wherein the first sidewall region is between and physically separates the spaced-apart non-sacrificial nanosheets from the first S/D region.

20. The method of claim 19 further comprising forming a second semiconductor device in a second region of the substrate, wherein forming the second semiconductor device comprises:

forming a second stack comprising second spaced-apart non-sacrificial nanosheets, spaced-apart inner spacers, and spaced-apart high-k metal gate (HKMG) structures; and

forming a second S/D region adjacent to the stack;

wherein the second S/D region is physically attached directly to ends of the second spaced-apart non-sacrificial nanosheets.

21. The method of claim 20 , wherein:

the bottom region comprises a substantially planar top surface;

the uniform thickness S/D template layer comprises a first type of semiconductor material;

the first S/D region comprises a second type of semiconductor materials; and

the second S/D region comprises a third type of semiconductor material.

22. The method of claim 21 , wherein an elemental composition of the first type of semiconductor material, an elemental composition of the second type of semiconductor material, and an elemental composition of the third type of semiconductor material are not the same.

23. A method of forming a semiconductor-based structure, the method comprising:

forming a stack over a substrate;

wherein the stack comprises spaced-apart non-sacrificial nanosheets and spaced-part high-k metal gate (HKMG) structures;

wherein the stack further comprises a stack sidewall comprising sidewalls of end regions of the spaced-apart non-sacrificial nanosheets and sidewalls of end regions of the spaced-apart HKMG structures;

forming a source or drain (S/D) region adjacent to the stack;

forming a protective liner on a gate spacer and on a top surface of the S/D region; and

forming a uniform thickness S/D template layer comprising a first sidewall region, a bottom region, and a second sidewall region;

wherein a lateral thickness of the first sidewall region, a vertical thickness of the bottom region, and a lateral thickness of the second sidewall region are substantially equal; and

wherein the first sidewall region is between and physically separates the spaced-apart non-sacrificial nanosheets from the S/D region.

24. The method of claim 23 , wherein:

the bottom region comprises a substantially planar top surface;

the uniform thickness S/D template layer comprises a first type of semiconductor material; and

the S/D region comprises a second type of semiconductor material.

25. The method of claim 24 , wherein an elemental composition of the first type of semiconductor material is different from an elemental composition of the second type of semiconductor material.

Assignments (1)

Continuity (1)

References Cited (12)