IP Library › Granted Patent US 12,268,026
Granted Patent B2
US 12,268,026 · App. 17/657,006 · Granted Apr 1, 2025

High aspect ratio contact structure with multiple metal stacks

Inventors: Junli Wang (Slingerlands, NY); Brent A Anderson (Jericho, VT); Terence Hook (Jericho Center, VT); Indira Seshadri (Niskayuna, NY); Albert M. Young (Fishkill, NY); Stuart Sieg (Albany, NY); Su Chen Fan (Cohoes, NY); Shogo Mochizuki (Mechanicville, NY)
Assignee: International Business Machines Corporation
H10D64/251H10D64/01
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,268,026
App. No.
17/657,006
Granted
Apr 1, 2025
Kind
B2
Abstract

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Claims (37)

1. A semiconductor structure, comprising:

a contact structure within a dielectric material, the contact structure including a top portion in a first contact trench, the first contact trench having a straight sidewall from a top to a bottom of the first contact trench, and a bottom portion in a second contact trench, the second contact trench being below the first contact trench and extended horizontally from the first contact trench, and the top portion of the contact structure including a tapering profile towards the bottom portion;

a first metal stack within the top portion of the contact structure;

a second metal stack within the bottom portion of the contact structure, the second metal stack filling the second contact trench from a bottom to a top of the second contact trench; and

an inner spacer surrounding the first metal stack from a top to a bottom of the first metal stack, wherein a maximum width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

2. The semiconductor structure of claim 1 , wherein the first metal stack is different in material from the second metal stack.

3. The semiconductor structure of claim 1 , wherein the first metal stack further comprises a first conformal metal liner interface.

4. The semiconductor structure of claim 1 , wherein the second metal stack comprises one or more layers of conductive materials.

5. The semiconductor structure of claim 1 , wherein the second metal stack further comprises a second conformal metal liner interface.

6. The semiconductor structure of claim 1 , wherein a taper angle of the top portion of the contact structure is less than a taper angle of the bottom portion measured from a horizontal plane.

7. The semiconductor structure of claim 1 , wherein the inner spacer comprises a dielectric spacer material.

8. The semiconductor structure of claim 1 , wherein an interface between the top portion and the bottom portion of the contact structure is located below a bottom surface of the inner spacer.

9. The semiconductor structure of claim 8 , wherein the maximum width of the bottom portion of the contact structure is greater than a width of the interface between the top portion and the bottom portion of the contact structure.

10. The semiconductor structure of claim 1 , wherein an interface between the top portion and the bottom portion of the contact structure is coplanar with a bottom surface of the inner spacer and an uppermost surface of the bottom portion of the contact structure.

11. A method of forming a semiconductor structure, comprising:

forming a contact structure within a dielectric material, the contact structure including a top portion and a bottom portion, the top portion including a tapering profile towards the bottom portion, wherein forming the contact structure further comprises:

conducting a first etching process within the dielectric material to form a first contact trench having a straight sidewall from a top to a bottom of the first contact trench;

depositing an inner spacer on the straight sidewall from the top to the bottom of the first contact trench;

conducting a second etching process to form a second contact trench below the first contact trench, wherein the second etching process is conducted until the second contact trench exposes an uppermost surface of an underlying active region; and

conducting a third etching process to horizontally extend the second contact trench;

depositing a second metal stack within the bottom portion of the contact structure and from a bottom to a top of the second contact trench; and

depositing a first metal stack within the top portion of the contact structure and within the first contact trench, the first metal stack being in contact with and surrounded by the inner spacer, wherein a maximum width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

12. The method of claim 11 , wherein the first metal stack further comprises a first conformal metal liner interface, the first metal stack being different in material from the second metal stack.

13. The method of claim 11 , wherein the second metal stack further comprises a second conformal metal liner interface, the second metal stack comprising one or more layers of conductive materials.

14. The method of claim 11 , wherein a taper angle of the top portion of the contact structure is less than a taper angle of the bottom portion of the contact structure measured from a horizontal plane.

15. The method of claim 11 , wherein the inner spacer comprises a dielectric spacer material.

16. The method of claim 11 , wherein an interface between the top portion and the bottom portion of the contact structure is located below a bottom surface of the inner spacer.

17. The method of claim 16 , wherein the maximum width of the bottom portion of the contact structure is greater than a width of the interface between the top portion and the bottom portion of the contact structure.

18. The method of claim 11 , wherein an interface between the top portion and the bottom portion of the contact structure is coplanar with a bottom surface of the inner spacer and an uppermost surface of the bottom portion of the contact structure.

19. A method of forming a semiconductor structure, comprising:

conducting a first etching process within a dielectric material to form a first contact trench having a straight sidewall from a top to a bottom of the first contact trench;

depositing an inner spacer on the straight sidewall from the top to the bottom of the first contact trench;

conducting a second etching process to form a second contact trench below the first contact trench with the first contact trench including a tapering profile towards the second contact trench, wherein the second etching process is conducted until the second contact trench exposes an uppermost surface of an underlying active region;

conducting a third etching process to horizontally extend the second contact trench, wherein a maximum width of the second contact trench is greater than a minimum width of the first contact trench;

depositing a second metal stack from a bottom to a top of the second contact trench; and

depositing a first metal stack within the first contact trench, the first metal stack being in contact with and surrounded by the inner spacer.

20. The method of claim 19 , wherein a taper angle of the first contact trench is less than a taper angle of the second contact trench measured from a horizontal plane.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2022
From: HOOK, TERENCE
To: INFINITE COMPUTER SOLUTIONS, INC.
Reel/Frame 059995/0887 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2022
From: INFINITE COMPUTER SOLUTIONS, INC.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 059995/0906 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2022
From: WANG, JUNLI; ANDERSON, BRENT A; SESHADRI, INDIRA; YOUNG, ALBERT M.; SIEG, STUART; FAN, SU CHEN; MOCHIZUKI, SHOGO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 059427/0300 →
Continuity (1)
Related Publication 20230317802A1 · Oct 5, 2023
References Cited (12)
US 8536656B2 · Ramachandran · 2013 [cited by applicant]
US 8841711B1 · Cai · 2014 [cited by applicant]
US 9054178B2 · Bohr · 2015 [cited by applicant]
US 9929046B2 · Cheng · 2018 [cited by applicant]
US 10242982B2 · Ruilong · 2019 [cited by applicant]
US 10312188B1 · Srivastava · 2019 [cited by examiner]
US 10832964B1 · Xie · 2020 [cited by applicant]
US 20170162444A1 · Ok · 2017 [cited by examiner]
US 20210134660A1 · Wang · 2021 [cited by examiner]
TW 673791B · 2019 [cited by applicant]
Lee, et al., “Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs”, Electronics 2021, 10, 1395, 7 pages. [cited by applicant]
Undisclosed, IP.com No. IPCOM000258215D, “Semiconductor Device and Method for Enabling Low Contact Resistance”, Apr. 18, 2019, 4 pages. [cited by applicant]