Silicon carbide wafer and semiconductor device
A silicon carbide wafer has one surface and the other surface opposite to the one surface. An average Rmax roughness of the one surface is 2.0 nm or less, and an average Ra roughness of the one surface is 0.1 nm or less. An edge region is a region in which a distance from an edge of the silicon carbide wafer toward a center is 5% to 75% of a radius of the silicon carbide wafer, and a central region is a region having a radius of 25% of the radius of the silicon carbide wafer at the center of the silicon carbide wafer. A difference between an average Rmax roughness of the edge region of the one surface and an average Rmax roughness of the central region of the one surface is 0.01 nm to 0.5 nm.
1. A silicon carbide wafer comprising one surface and the other surface opposite to the one surface,
wherein an average Rmax roughness of the one surface is 2.0 nm or less,
wherein an average Ra roughness of the one surface is 0.1 nm or less,
wherein an edge region is a region in which a distance from an edge of the silicon carbide wafer toward a center is 5% to 75% of a radius of the silicon carbide wafer,
wherein a central region is a region having a radius of 25% of the radius of the silicon carbide wafer at the center of the silicon carbide wafer, and
wherein a difference between an average Rmax roughness of the edge region of the one surface and an average Rmax roughness of the central region of the one surface is 0.01 nm to 0.5 nm.
2. The silicon carbide wafer of claim 1 , wherein a total light transmittance for a D65 standard light source is 10% to 40%.
3. The silicon carbide wafer of claim 1 , wherein the average Rmax roughness of the one surface is 1.5 nm or less.
4. The silicon carbide wafer of claim 1 , wherein the difference between the average Ra roughness of the edge region of the one surface and the average Ra roughness of the central region of the one surface is 0.08 nm or less.
5. The silicon carbide wafer of claim 1 , wherein a haze for a D65 standard light source is 0.3% to 0.5%.
6. The silicon carbide wafer of claim 1 , wherein the average Ra roughness of the silicon carbide wafer is 0.07 nm or less.
7. The silicon carbide wafer of claim 1 , wherein the one surface is a Si surface where silicon atoms appear more mainly than carbon atoms.
8. The silicon carbide wafer of claim 1 , wherein a diameter of the silicon carbide wafer is 4 inches or more and comprises 4H-silicon carbide.
9. An epitaxial wafer comprising:
a silicon carbide wafer of claim 1 ; and
an epitaxial layer that is formed on the one surface of the silicon carbide wafer.
10. A semiconductor device comprising:
a silicon carbide wafer of claim 1 ;
an epitaxial layer that is formed on the one surface of the silicon carbide wafer;
a barrier region disposed opposite to the silicon carbide wafer with the epitaxial layer interposed therebetween;
a source electrode in contact with the epitaxial layer;
a gate electrode disposed on the barrier region; and
a drain electrode disposed on the other surface of the silicon carbide wafer.