Memory organization for multi-mode support
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
1. A layout of a circuit board, comprising:
a first memory package and a second memory package, each comprising:
first, second, third, and fourth channels arranged consecutively in a clockwise direction, each of the first, second, third, and fourth channels having memory arrays,
wherein the first and fourth channels comprise initiator channels and exhibit vertical symmetry around a horizontal middle line;
the second and third channels comprise target channels and exhibit vertical symmetry around the horizontal middle line;
the first and second channels exhibit horizontal symmetry around a vertical center line; and
the third and fourth channels further exhibit horizontal symmetry around the vertical center line,
wherein in a first mode, the initiator channels and the target channels are independently accessible, and in a second mode, the first channel controls accesses to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
2. The circuit board of claim 1 , wherein:
the first memory package is arranged such that the first channel of the first memory package is in a top left position with respect to a reference line of the circuit board, and the second memory package is arranged horizontally adjacent to the first memory package such that the first channel of the second memory package is in a bottom right position with respect to the reference line of the circuit board of the circuit board.
3. The circuit board of claim 1 , further comprising:
an integrated circuit processor die comprising a memory controller having first and second memory controller physical channel interfaces coupled to the first and fourth channels of the first memory package, respectively, and third and fourth memory controller physical channel interfaces coupled to the fourth and first channels of the second memory package, respectively.
4. The circuit board of claim 3 , wherein:
the integrated circuit processor die comprises a graphics processing unit.
5. The circuit board of claim 3 , further comprising:
a non-crossing routing between the first and second memory controller physical channel interfaces and the first and fourth channels of the first memory package, respectively, and between the third and fourth memory controller physical channel interfaces and the fourth and first channels of the second memory package, respectively.
6. The circuit board of claim 1 , wherein:
the first channel of each of the first and second memory packages has a first plurality of signals in a first flat order from left to right; and
the second channel of each of the first and second memory packages has a second plurality of signals corresponding to the first plurality of signals in a reverse order.
7. The circuit board of claim 6 , wherein:
the third channel of each of the first and second memory packages has a third plurality of signals in a second flat order from left to right; and
the fourth channel of a respective one of the first and second memory packages has a fourth plurality of signals corresponding to the third plurality of signals in the reverse order.
8. The circuit board of claim 6 , wherein:
the first plurality of signals of each of the first and second memory packages comprises read clock signals, data signals, and command and address signals.
9. The circuit board of claim 1 , wherein:
the first memory package is arranged such that the first channel of the first memory package is in a top left position with respect to a reference line of the circuit board and is located on a first surface of the circuit board, and the second memory package is arranged such that the first channel of the second memory package is in a top right position with respect to the reference line of the circuit board and is located on a second surface of the circuit board opposite the first surface.
10. The circuit board of claim 9 , further comprising:
an integrated circuit processor die comprising a memory controller having first and second memory controller physical channel interfaces coupled to the first and fourth channels of the first memory package, respectively, and third and fourth memory controller physical channel interfaces coupled to the fourth and first channels of the second memory package, respectively.
11. The circuit board of claim 10 , wherein:
the integrated circuit processor die comprises a graphics processing unit.
12. The circuit board of claim 10 , further comprising:
a non-crossing routing between the first and second memory controller physical channel interfaces and the first and fourth channels of the first memory package, respectively, and between the third and fourth memory controller physical channel interfaces and the fourth and first channels of the second memory package, respectively.
13. The circuit board of claim 9 , wherein:
the first channel of each of the first and second memory packages has a first plurality of signals in a first flat order from left to right; and
the second channel of each of the first and second memory packages has a second plurality of signals corresponding to the first plurality of signals in a reverse order.
14. The circuit board of claim 13 , wherein:
the third channel of each of the first and second memory packages has a third plurality of signals in a second flat order from left to right; and
the fourth channel of a respective one of the first and second memory packages has a fourth plurality of signals corresponding to the third plurality of signals in the reverse order.
15. The circuit board of claim 13 , wherein:
the first plurality of signals of each of the first and second memory packages comprises read clock signals, data signals, and command and address signals.