System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design
View Patent ↗A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.
1. A method comprising:
conducting a first co-simulation of a first design stage for a System on Chip (SOC) and an Integrated Voltage Regulator (IVR);
determining whether the SOC and the IVR pass the first co-simulation;
if the SOC and the IVR do not pass the first co-simulation, then refining specification data of the SOC and/or refining first design data of the IVR and repeating the first co-simulation;
if the SOC and the IVR pass the first co-simulation, then conducting a second co-simulation of a second design stage for the SOC and the IVR;
determining whether the SOC and the IVR pass the second co-simulation;
if the SOC and the IVR do not pass the second co-simulation, then refining the specification data of the SOC and/or refining the design data of the IVR and repeating the second co-simulation;
if the SOC and the IVR pass the second co-simulation, then conducting a third co-simulation of a third design stage for the SOC and the IVR;
determining whether the SOC and the IVR pass the third co-simulation;
if the SOC and the IVR do not pass the third co-simulation, then refining the specification data of the SOC and/or refining the design data of the IVR and repeating the third co-simulation;
if the SOC and the IVR pass the third co-simulation, then finalizing designs for the SOC and the IVR.
2. The method of claim 1 , wherein the first design stage comprises a Register-Transfer Level (RTL) design stage.
3. The method of claim 1 , wherein the second design stage comprises a pre-simulation design stage of the SOC.
4. The method of claim 1 , wherein the third design stage comprises a post-simulation design stage of the SOC.
5. The method of claim 1 , further comprising:
extracting a first current profile model corresponding to the SOC at the first design stage, wherein the first co-simulation is based on the extracted first current profile model;
extracting a second current profile model corresponding to the SOC at the second design stage, wherein the second co-simulation is based on the extracted second current profile model; and
extracting a third current profile model corresponding to the SOC at the third design stage, wherein the third co-simulation is based on the extracted third current profile model.
6. The method of claim 5 , wherein at least one of the first current profile model, the second current profile model, and the third current profile model includes a decoupling capacitor model.
7. The method of claim 5 , wherein at least one of the first current profile model, the second current profile model, and the third current profile model includes a power grid model.
8. The method of claim 7 , wherein the power grid model corresponds to at least one of the bumps and Through-Silicon Vias (TSV).
9. The method of claim 7 , wherein the power grid model corresponds to a power mesh of the SOC.
10. The method of claim 5 , wherein at least one of the first current profile model, the second current profile model, and the third current profile model comprises a Piecewise Linear (PWL) description of an SOC I(t) extracted from a dynamic power waveform.
11. The method of claim 10 , further comprising selecting a Tstep for the SOC I(t) comprising min (0.1×Tperiod, Trise/Tfall).
12. The method of claim 1 , wherein the IVR comprises a switching regulator.
13. The method of claim 1 , wherein the IVR comprises a low-dropout (LDO) regulator.
14. A method comprising:
determining a first decoupling capacitor model for a System on Chip (SOC);
extracting a first current profile model based on the first decoupling capacitor model at a first design stage of the SOC;
conducting a first co-simulation based on the extracted first current profile model and a first design data of an Integrated Voltage Regulator (IVR);
determining whether the SOC and the IVR pass the first co-simulation;
if the SOC and the IVR do not pass the first co-simulation, then refining the first decoupling capacitor model and repeating the first co-simulation;
if the SOC and the IVR pass the first co-simulation, then extracting a second current profile model based on a second decoupling capacitor model at a second design stage of the SOC;
conducting a second co-simulation based on the extracted second current profile model and a second design data of the IVR;
determining w ether the SOC and the IVR pass the second co-simulation;
if the SOC and the IVR do not pass the second co-simulation, then refining the second decoupling capacitor model and repeating the second co-simulation;
if the SOC and the IVR pass the second co-simulation, then extracting a third current profile model based on a third decoupling capacitor model at a third design stage of the SOC;
conducting a third co-simulation based on the extracted third current profile model and a third design data of the IVR;
determining whether the SOC and the IVR pass the third co-simulation;
if the SOC and the IVR do not pass the third co-simulation, then refining the third decoupling capacitor model and repeating the third co-simulation;
if the SOC and the IVR pass the third co-simulation, then finalizing designs for the SOC and the IVR.
15. The method of claim 14 , wherein the first design stage comprises a Register-Transfer Level (RTL) design state, the second design stage comprises a pre-simulation design stage of the SOC, and the third design stage comprises a post-simulation design stage of the SOC.
16. The method of claim 14 , further comprising:
determining a power grid model for the SOC;
wherein the extracted first current profile model is further based on the power grid model.
17. The method of claim 14 , further comprising:
determining a dynamic power extraction model for the SOC;
wherein the extracted first current profile model is further based on the dynamic power extraction model.
18. A method comprising:
determining a first dynamic power waveform of a System on Chip (SOC) design at a first design stage of the SOC;
extracting a first Piecewise Linear (PWL) description of an SOC I(t) from the dynamic power waveform to determine a first current profile model of the SOC;
conducting a first co-simulation based on the first current profile model and a first design data of an Integrated Voltage Regulator (IVR);
determining whether the SOC and the IVR pass the second co-simulation;
if the SOC and the IVR do not pass the first co-simulation, then refining the first current profile model and repeating the first co-simulation;
if the SOC and the IVR pass the first co-simulation, then determining a second dynamic power waveform at a second design stage of the SOC, and extracting a second PWL description of the SOC I(t) from the second dynamic power waveform to determine a second current profile model of the SOC;
conducting a second co-simulation based on the second current profile model and a second design data of the IVR;
if the SOC and the IVR do not pass the second co-simulation, then refining the second current profile model and repeating the second co-simulation;
if the SOC and the IVR pass the second co-simulation, then determining a third dynamic power waveform at a third design stage of the SOC, and extracting a third PWL description of the SOC I(t) from the third dynamic power waveform to determine a third current profile model of the SOC;
conducting a third co-simulation based on the third current profile model and a third design data of the IVR;
if the SOC and the IVR do not pass the third co-simulation, then refining the third current profile model and repeating the third co-simulation, and
if the SOC and the IVR pass the third co-simulation, then finalizing designs for the SOC and the IVR.
19. The method of claim 18 , wherein the first design stage comprises a Register Transfer Level (RTL) design stage, the second design stage comprises a pre-simulation design stage of the SOC, and the third design stage comprises a post-simulation design stage of the SOC.
20. The method of claim 18 , wherein the IVR comprises one of a switching regulator or a low-dropout (LDO) regulator.