Method of fabricating thin, crystalline silicon film and thin film transistors
A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the substrate and nickel patterns, and forming an intrinsic silicon layer on the phosphorus doped silicon layer. Alternatively, the intrinsic silicon layer can be formed on the substrate, the phosphorus doped silicon layer on the intrinsic silicon layer, and the nickel patterns on the phosphorus doped silicon layer. The structure is annealed to crystallize the phosphorus doped silicon and intrinsic silicon layers. A method of forming a crystalline silicon layer of a TFT device includes forming a first silicon film, forming a phosphorus doped silicon film on the first silicon film, forming a nickel film on the phosphorus doped silicon film, and annealing the structure to crystallize the phosphorus doped silicon and first silicon films. The first silicon and phosphorous doped silicon films are amorphous at formation.
1. A method of producing a polycrystalline silicon thin film transistor, comprising:
forming nickel patterns on a substrate;
forming a phosphorus doped silicon layer over the substrate and the nickel patterns, the phosphorus doped silicon layer being amorphous at formation;
forming a first silicon layer on the phosphorus doped silicon layer, the first silicon layer being amorphous at formation, the first silicon layer including intrinsic silicon;
annealing the phosphorus doped silicon layer, the first silicon layer, and the nickel patterns to cause crystallization of the phosphorus doped silicon layer, and the first silicon layer, wherein the crystallization propagates by a combination of lateral crystal growth between the nickel patterns and vertical crystal growth to crystallize the phosphorus doped silicon layer, and the first silicon layer.
2. The method of claim 1 wherein doping of the first silicon layer to form source drain regions is done with a p-type dopant.
3. The method of claim 1 , further comprising forming an additional p-type silicon layer between the phosphorus doped silicon layer and the first silicon layer, the p-type silicon layer being amorphous at formation, wherein the annealing is performed to crystallize the phosphorus doped silicon layer, the p-type silicon layer, and the first silicon layer, such that the crystallization propagates by a combination of lateral crystal growth between the nickel patterns and vertical crystal growth to crystallize the phosphorus doped silicon layer, the p-type silicon layer and the first silicon layer, wherein a n-type dopant is used in doping the first silicon layer in selected areas to form the source and drain regions.
4. The method of claim 1 wherein barrier layer patterns are formed over a top surface of the nickel patterns to minimize nickel incorporation in the phosphorus doped silicon layer and the first silicon layer.
5. The method of claim 1 , wherein doping the first silicon layer to form source-drain regions is performed by one or more doping steps selected from a group of doping steps comprising doping before formation of the gate insulator layer, doping after formation of the gate insulator layer, and doping after formation of the gate electrode pattern.
6. The method of claim 1 , wherein the annealing temperature is 500 degree C. or lower.
7. The method of claim 1 , wherein, the phosphorus doped silicon layer has a thickness in the range of 500-1500 angstroms and the first silicon layer has a thickness in the range of 200-1000 angstroms.
8. The method of claim 1 , further comprising forming a second silicon layer between the substrate and the nickel patterns, the second silicon layer being amorphous at the formation, wherein the annealing is performed to cause the crystallization of the phosphorus doped silicon layer, the first silicon layer and the second silicon layer, wherein the silicon crystal growth propagates by a combination of lateral crystal growth between the nickel patterns and vertical crystal growth to crystallize the phosphorus doped silicon layer, the first silicon layer and the second silicon layer.
9. The method of claim 1 , further comprising forming a silicon layer between the nickel patterns and the phosphorus doped silicon layer, the silicon layer being amorphous at the formation, wherein as a result of annealing the phosphorus doped silicon layer, the first silicon layer, and the silicon layer crystallize, wherein silicon crystal growth propagates by a combination of lateral crystal growth and vertical crystal growth.
10. The method of claim 1 , further comprising:
forming a gate insulator layer over the first silicon layer;
forming a gate electrode pattern over the gate insulator layer; and
doping into the selected areas of the first silicon layer to form source and drain regions separated by a channel region.
11. A method of forming a crystalline silicon layer of a TFT device having a gate, a gate insulator, and an active layer, the active layer comprising source, drain, and channel regions formed in the crystalline silicon layer, the method comprising:
forming a first silicon film, the first silicon film being amorphous at formation;
forming a phosphorus doped silicon film on the first silicon film, the phosphorous doped silicon film being amorphous at formation;
forming a nickel film on the phosphorus doped silicon film; and
annealing the structure to crystallize the phosphorus doped silicon film and the first silicon film, wherein crystallization propagates by a combination of lateral crystal growth and vertical crystal growth.
12. The method of claim 11 , further comprising forming a second silicon film on the nickel film and the phosphorus doped silicon film, wherein the second silicon film is amorphous at formation, wherein the annealing is performed to cause the crystallization of the phosphorus doped silicon film, the first silicon film, and the second silicon film, wherein the silicon crystal growth propagates by a combination of lateral crystal growth between the nickel patterns and vertical crystal growth to crystallize the phosphorus doped silicon film, the first silicon film and the second silicon film, and after crystallization, removing the phosphorus doped silicon film and the second silicon film from the first silicon film.
13. The method of claim 11 , wherein barrier layer patterns are formed between the nickel film and the phosphorus doped film to minimize nickel incorporation in the phosphorus doped silicon layer and the first silicon film.
14. The method of claim 11 , wherein the annealing temperature is 500 degree C. or lower.
15. The method of claim 11 , where the thickness of the first silicon layer is in the range 750-2000 angstroms, and that of the phosphorus doped silicon layer is 500-1500 angstroms.
16. The method of claim 11 , wherein the nickel film is formed discontinuously on the phosphorus doped film.
17. The method of claim 11 , wherein the phosphorus doped film is formed discontinuously on the first silicon film.
18. The method of claim 11 , further comprising forming a second silicon film between the nickel film and the phosphorus doped silicon film, wherein the second silicon film is amorphous at formation, wherein the annealing is performed to crystallize the phosphorus doped silicon film, the first silicon film, and the second silicon film, wherein the silicon crystal growth propagates by a combination of lateral crystal growth and vertical crystal growth.
19. The method of claim 11 , further comprising removing at least a portion of the phosphorus doped silicon film.
20. The method of claim 11 , wherein the first silicon film includes intrinsic silicon.
21. A method of forming polycrystalline silicon TFT, comprising:
forming a first intrinsic silicon film on a substrate, the first intrinsic silicon film being amorphous initially;
forming a phosphorus doped silicon film on the first intrinsic silicon film, the phosphorous doped silicon film being amorphous initially;
forming nickel patterns on the phosphorus doped silicon film;
annealing the structure to cause crystallization of the phosphorus doped silicon film and the first intrinsic silicon film, wherein the crystallization propagates by a combination of lateral crystal growth between the nickel patterns and vertical crystal growth;
removing the phosphorus doped silicon film from the first intrinsic silicon film after the crystallization;
forming a gate insulator film over the crystallized first intrinsic silicon film;
forming a gate electrode pattern over the gate insulator film; and
doping into the selected areas of the crystallized first intrinsic silicon film to form source and drain regions separated by a channel region.
22. A method of forming a polycrystalline silicon TFT, the method comprising:
forming a first silicon layer supported by a substrate, the first silicon layer being amorphous at formation, the first silicon layer including intrinsic silicon;
forming a phosphorus doped silicon layer supported by the substrate, the phosphorous doped silicon layer being amorphous at formation;
forming a nickel film supported by the substrate, the phosphorous doped silicon layer being between the first silicon layer and the nickel film; and
annealing the phosphorus doped silicon layer, the first silicon layer, and the nickel film to cause crystallization of the phosphorus doped silicon layer and the first silicon layer,
wherein the crystallization propagates by a combination of lateral crystal growth and vertical crystal growth to crystallize the phosphorus doped silicon layer and the first silicon layer.