Semiconductor memory device
A semiconductor memory device includes memory block regions arranged in a first direction, a hook-up region arranged in the first direction with respect to memory block regions, and a wiring region extending in the first direction and arranged with memory block regions and the hook-up region in a second direction. Each of memory block regions includes memory strings extending in the first direction and arranged in the second direction and a first wiring extending in the second direction and connected to memory strings in common. The wiring region includes a second wiring extending in the first direction and connected to first wirings corresponding to memory block regions in common. The hook-up region includes a third wiring connected to the second wiring and a contact electrode extending in a third direction and connected to the third wiring.
1. A semiconductor memory device comprising:
a plurality of memory block regions arranged in a first direction;
a hook-up region arranged in the first direction with respect to the plurality of memory block regions; and
a wiring region extending in the first direction, the wiring region being arranged with the plurality of memory block regions and the hook-up region in a second direction intersecting with the first direction, wherein
each of the plurality of memory block regions includes:
a plurality of memory strings that extend in the first direction and are arranged in the second direction; and
a first wiring that extends in the second direction and is connected to the plurality of memory strings in common,
the wiring region includes a second wiring that extends in the first direction and is connected to a plurality of the first wirings corresponding to the plurality of memory block regions in common, and
the hook-up region includes:
a third wiring electrically connected to the second wiring; and
a contact electrode that extends in a third direction intersecting with the first direction and the second direction and is connected to the third wiring.
2. The semiconductor memory device according to claim 1 , wherein
the contact electrode includes:
a first part extending in the third direction; and
a second part connected to the first part, the second part being connected to a side surface in the first direction or the second direction of the third wiring, and
when a cross-sectional surface that extends in the first direction and the second direction and includes the second part of the contact electrode is assumed to be a first cross-sectional surface, in the first cross-sectional surface:
a part of an outline of the second part is disposed along a circumference of a first circle; and
a part other than the part of the outline of the second part is disposed inside the first circle.
3. The semiconductor memory device according to claim 1 , comprising
a plurality of memory layers arranged in the third direction, wherein
each of the plurality of memory layers includes the plurality of memory strings, a plurality of the first wirings, the second wiring, and the third wiring, and
the hook-up region includes a plurality of the contact electrodes corresponding to the plurality of memory layers.
4. The semiconductor memory device according to claim 3 , wherein
each of the plurality of memory layers includes a signal amplifier circuit.
5. The semiconductor memory device according to claim 3 , wherein
the hook-up region includes a first voltage supply line that extends in the third direction,
in the hook-up region, each of the plurality of memory layers includes:
a fourth wiring electrically connected between the second wiring and the third wiring;
a first transistor electrically connected between the third wiring and the fourth wiring;
a second transistor electrically connected between the third wiring and the first voltage supply line; and
a third transistor electrically connected between the second transistor and the first voltage supply line, wherein
the fourth wiring functions as a gate electrode of the third transistor.
6. The semiconductor memory device according to claim 5 , wherein
the hook-up region includes a first electrode and a second electrode that extend in the third direction, and
in the plurality of memory layers, the first electrode and the second electrode function as gate electrodes of the first transistor and the second transistor respectively.
7. The semiconductor memory device according to claim 6 , wherein
in the hook-up region, each of the plurality of memory layers includes:
a first semiconductor layer that includes a part opposed to the fourth wiring;
a second semiconductor layer that is opposed to the first electrode; and
a third semiconductor layer that is opposed to the second electrode.
8. The semiconductor memory device according to claim 7 , wherein
the hook-up region includes a second voltage supply line that extends in the third direction and is connected to the first semiconductor layer.
9. A semiconductor memory device comprising:
a plurality of memory cells arranged in a first direction;
a plurality of first wirings arranged in the first direction and being electrically connected to the plurality of memory cells; and
a contact electrode extending in the first direction and being connected to any of the plurality of first wirings, wherein
the contact electrode includes:
a first part that extends in the first direction; and
a second part connected to the first part, the second part being connected to a side surface in a second direction intersecting with the first direction of any of the plurality of first wirings, and
when a cross-sectional surface that is perpendicular to the first direction and includes the second part of the contact electrode is assumed to be a first cross-sectional surface, in the first cross-sectional surface:
a part of an outline of the second part is disposed along a circumference of a first circle; and
a part other than the part of the outline of the second part is disposed inside the first circle.
10. The semiconductor memory device according to claim 9 , wherein
when a cross-sectional surface that is perpendicular to the first direction and includes the first part of the contact electrode is assumed to be a second cross-sectional surface:
an area of the first part in the second cross-sectional surface is smaller than an area of the second part in the first cross-sectional surface.
11. The semiconductor memory device according to claim 9 , comprising
a plurality of memory layers arranged in the first direction, wherein
each of the plurality of memory layers includes the plurality of memory cells and the plurality of first wirings, and
each of the plurality of memory layers includes a signal amplifier circuit.
12. The semiconductor memory device according to claim 11 , wherein
in one memory layer among the plurality of memory layers,
the signal amplifier circuit is electrically connected between at least one of the plurality of first wirings and the plurality of memory cells.
13. A semiconductor memory device comprising:
a plurality of memory layers arranged in a first direction;
a plurality of contact electrodes that extend in the first direction and are connected to the plurality of memory layers; and
a first voltage supply line that extends in the first direction and is connected to the plurality of memory layers, wherein
each of the plurality of memory layers includes:
a memory cell;
a first wiring electrically connected to the memory cell;
a second wiring electrically connected to any of the plurality of contact electrodes;
a first transistor electrically connected between the first wiring and the second wiring;
a second transistor electrically connected between the second wiring and the first voltage supply line; and
a third transistor electrically connected between the second transistor and the first voltage supply line, wherein
the first wiring functions as a gate electrode of the third transistor.
14. The semiconductor memory device according to claim 13 , comprising
a first electrode and a second electrode that extend in the first direction and are connected to the plurality of memory layers, wherein
the first electrode and the second electrode function as gate electrodes of the first transistor and the second transistor respectively.
15. The semiconductor memory device according to claim 14 , wherein
each of the plurality of memory layers includes:
a first semiconductor layer including a part opposed to the first wiring;
a second semiconductor layer opposed to the first electrode; and
a third semiconductor layer opposed to the second electrode.
16. The semiconductor memory device according to claim 15 , comprising
a second voltage supply line extending in the first direction and being connected to the first semiconductor layer.
17. The semiconductor memory device according to claim 15 , wherein
each of the plurality of memory layers includes at least two gate insulating layers in contact with the first semiconductor layer, and
the first semiconductor layer is opposed to the first wiring via the at least two gate insulating layers.
18. The semiconductor memory device according to claim 13 , wherein
each of the plurality of contact electrodes includes:
a first part extending in the first direction; and
a second part connected to the first part, the second part being connected to a side surface in a second direction intersecting with the first direction of any of the plurality of first wirings, and
when a cross-sectional surface that is perpendicular to the first direction and includes the second parts of the plurality of contact electrodes is assumed to be a first cross-sectional surface, in the first cross-sectional surface:
a part of an outline of the second part is disposed along a circumference of a first circle; and
a part other than the part of the outline of the second part is disposed inside the first circle.
19. The semiconductor memory device according to claim 18 , wherein
when a cross-sectional surface that is perpendicular to the first direction and includes the first part of the contact electrode is assumed to be a second cross-sectional surface:
an area of the first part in the second cross-sectional surface is smaller than an area of the second part in the first cross-sectional surface.