Granted Patent B2

US 12,272,647 · App. 17/720,642 · Granted Apr 8, 2025

Inventors: Byounghak Hong (Albany, NY); Kang-ill Seo (Albany, NY); Jason Martineau (Fremont, CA)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

H01L23/5286H01L24/08H01L24/80H01L25/0657H01L25/50H01L2224/08145H01L2224/80895H01L2224/80896

Abstract

Claims (52)

1. A three-dimensionally (3D) stacked semiconductor chip architecture comprising:

a first semiconductor chip comprising:

a first semiconductor layer;

a first front-end-of-line (FEOL) layer provided on a first side of the first semiconductor layer;

a first middle-of-line (MOL) layer provided on the first FEOL layer;

a first back-end-of-line (BEOL) layer provided on the first MOL layer;

a first power rail layer provided on a second side of the first semiconductor layer;

a second semiconductor chip comprising:

a second semiconductor layer;

a second FEOL layer provided on a first side of the second semiconductor layer;

a second MOL layer provided on the second FEOL layer;

a second BEOL layer provided on the second MOL layer;

a second power rail layer provided on a second side of the second semiconductor layer,

wherein the first power rail layer and the second power rail layer contact each other,

wherein the first power rail layer comprises a first power rail configured to distribute power, and the second power rail layer comprises a second power rail configured to distribute power, and

wherein an entirety of the first power rail is parallel to an entirety of the second power rail.

2. The 3D stacked semiconductor chip architecture of claim 1 ,

wherein the first semiconductor chip further comprises a first interdielectric layer on side surfaces of the first power rail,

wherein the second semiconductor chip further comprises a second interdielectric layer on side surfaces of the second power rail, and

wherein the first interdielectric layer directly contacts the second interdielectric layer.

3. The 3D stacked semiconductor chip architecture of claim 2 , wherein the first power rail contacts the second power rail.

4. The 3D stacked semiconductor chip architecture of claim 2 , wherein the first power rail protrudes from a surface on the second side of the first semiconductor layer in a vertical direction, and

wherein the second power rail comprises openings that extend through a portion of the second semiconductor layer in the vertical direction.

5. The 3D stacked semiconductor chip architecture of claim 4 , wherein a shape of the first power rail corresponds to a shape of the openings, and

wherein the first power rail is inserted into an opening of the openings and contacts the second power rail.

6. The 3D stacked semiconductor chip architecture of claim 5 , wherein the first power rail has a circular shape, and

wherein the second power rail has a ring shape and comprises the opening having a circular shape, the circular shape of the opening corresponding to the circular shape of the first power rail.

7. The 3D stacked semiconductor chip architecture of claim 5 , wherein the first power rail has a rectangular shape,

wherein the second power rail has a rectangular shape, and

wherein the opening having a rectangular shape is between the second power rail and an adjacent second power rail, the rectangular shape of the opening corresponding to the rectangular shape of the first power rail.

8. The 3D stacked semiconductor chip architecture of claim 2 , wherein the first semiconductor layer and the second semiconductor layer comprise an inter-dielectric layer.

9. The 3D stacked semiconductor chip architecture of claim 2 , wherein the first power rails and the second power rails comprise one of copper (Cu), cobalt (Co), tungsten (W), and ruthenium (Ru).

10. The 3D stacked semiconductor chip architecture of claim 1 , wherein the first semiconductor chip and the second semiconductor chip are back side power distribution network (BSPDN) semiconductor chips.

11. A three-dimensionally (3D) stacked semiconductor chip architecture comprising:

a first semiconductor chip comprising:

a first semiconductor layer;

a first front-end-of-line (FEOL) layer provided on a first side of the first semiconductor layer;

a first middle-of-line (MOL) layer provided on the first FEOL layer;

a first back-end-of-line (BEOL) layer provided on the first MOL layer;

a plurality of first power rails provided on a second side of the first semiconductor layer, the plurality of first power rails configured to distribute power; and

a second semiconductor chip provided on the first semiconductor chip, the second semiconductor chip comprising:

a second semiconductor layer;

a second FEOL layer provided on a first side of the second semiconductor layer;

a second MOL layer provided on the second FEOL layer;

a second BEOL layer provided on the second MOL layer;

a plurality of second power rails provided on a second side of the second semiconductor layer, the plurality of second power rails configured to distribute power,

wherein the plurality of first power rails and the plurality of second power rails contact each other,

wherein the plurality of first power rails protrude from a surface on the second side of the first semiconductor layer in a vertical direction,

wherein the plurality of second power rails comprise openings that extend through a portion of the second semiconductor layer in the vertical direction, and

wherein the first semiconductor chip further comprises a first interdielectric layer on side surfaces of the plurality of first power rails,

wherein the second semiconductor chip further comprises a second interdielectric layer on side surfaces of the plurality of second power rails, and

wherein the first interdielectric layer directly contacts the second interdielectric layer.

Assignments (1)

Continuity (2)

References Cited (26)