Semiconductor and circuit structures, and related methods
A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.
1. A circuit structure, comprising:
a first die area comprising an output logic gate;
a second die area comprising a circuit and an input logic gate; and
a die-to-die interconnect;
wherein the input logic gate comprises a transistor, wherein the circuit is connected between the die-to-die interconnect and a gate region of the transistor;
wherein the circuit comprises a MOS transistor,
wherein a first source/drain region of the MOS transistor is connected to the die-to-die interconnect.
2. The circuit structure of claim 1 ,
wherein the MOS transistor is a PMOS transistor,
wherein the circuit comprises an NMOS transistor,
wherein the first source/drain region of the PMOS transistor is connected to a first source/drain region of the NMOS transistor, and
wherein a second source/drain region of the PMOS transistor is connected to a second source/drain region of the NMOS transistor and the gate region of the transistor.
3. The circuit structure of claim 1 ,
wherein the MOS transistor is a first PMOS transistor,
wherein the circuit comprises a first NMOS transistor, a second PMOS transistor and a second NMOS transistor,
wherein a first source/drain region of the second PMOS transistor is connected to a first source/drain region of the second NMOS transistor and the gate region of the transistor.
4. The circuit structure of claim 3 , wherein a second source/drain region of the first PMOS transistor is connected to a second source/drain region of the first NMOS transistor,
wherein a second source/drain region of the second PMOS transistor is connected to a second source/drain region of the second NMOS transistor,
wherein the second source/drain region of the first PMOS transistor is connected to the second source/drain region of the second PMOS transistor.
5. The circuit structure of claim 3 , wherein a second source/drain region of the first PMOS transistor is connected to a second source/drain region of the second PMOS transistor,
a second source/drain region of the first NMOS transistor is connected to a second source/drain region of the second NMOS transistor.
6. The circuit structure of claim 1 , wherein the die-to-die interconnect is electrically connected to the gate region of the transistor only via the circuit.
7. The circuit structure of claim 1 , wherein the first die area comprises a first standard cell that comprises the output logic gate.
8. The circuit structure of claim 7 , wherein the second die area comprises a second standard cell that comprises the input logic gate.
9. The circuit structure of claim 8 , wherein the second standard cell comprises the circuit.
10. The circuit structure of claim 1 , wherein the first die and the second die are in a same package.
11. The circuit structure of claim 10 , wherein the package is a chip-on-wafer-on-substrate (CoWoS) package or an integrated fan-out (InFO) package.
12. A semiconductor structure, comprising:
a first die;
a second die comprising a first transistor;
a die-to-die interconnect electrically coupling the first die and the second die; and
a semi-conductive path between the die-to-die interconnect and a gate region of the first transistor,
wherein a discharge path is electrically connected in parallel to the semi-conductive path, wherein the discharge path is configured to be electrically conductive in response to a presence of an amount of electric charges sufficient to break down a gate dielectric of the first transistor, and
wherein the semi-conductive path is configured to be electrically conductive in response to a presence of a control voltage being greater than a threshold voltage, and is configured to be electrically non-conductive in response to an absence of the control voltage being greater than the threshold voltage.
13. The semiconductor structure of claim 12 , wherein the second die comprises:
a second transistor comprising a gate region, a first source/drain region and a second source/drain region, wherein the second transistor is connected between the die-to-die interconnect and the gate terminal of the first transistor.
14. The semiconductor structure of claim 13 , wherein the first source/drain region of the second transistor is connected to the die-to-die interconnect.
15. The semiconductor structure of claim 14 , wherein the first source/drain region of the second transistor is conductively connected to the die-to-die interconnect.
16. A circuit structure, comprising:
a first die area comprising a MOS transistor and an input logic gate having a gate region; and
a die-to-die interconnect,
wherein the MOS transistor is connected between the die-to-die interconnect and the gate region of the input logic gate, and wherein a first source/drain region of the MOS transistor is connected to the die-to-die interconnect.
17. The circuit structure of claim 16 ,
wherein the MOS transistor is a PMOS transistor,
wherein the first die area further comprises an NMOS transistor,
wherein the first source/drain region of the PMOS transistor is connected to a first source/drain region of the NMOS transistor, and
wherein a second source/drain region of the PMOS transistor is connected to a second source/drain region of the NMOS transistor and the gate region of the input logic gate.
18. The circuit structure of claim 16 ,
wherein the MOS transistor is a first PMOS transistor,
wherein the first die area further comprises a first NMOS transistor, a second PMOS transistor and a second NMOS transistor,
wherein a first source/drain region of the second PMOS transistor is connected to a first source/drain region of the second NMOS transistor and the gate region of the input logic gate.
19. The circuit structure of claim 18 ,
wherein a second source/drain region of the first PMOS transistor is connected to a second source/drain region of the first NMOS transistor,
wherein a second source/drain region of the second PMOS transistor is connected to a second source/drain region of the second NMOS transistor,
wherein the second source/drain region of the first PMOS transistor is connected to the second source/drain region of the second PMOS transistor.
20. The circuit structure of claim 18 ,
wherein a second source/drain region of the first PMOS transistor is connected to a second source/drain region of the second PMOS transistor,
a second source/drain region of the first NMOS transistor is connected to a second source/drain region of the second NMOS transistor.