IP Library › Granted Patent US 12,273,095
Granted Patent B2
US 12,273,095 · App. 17/245,901 · Granted Apr 8, 2025

Wideband filter with resonators and inductors

Inventors: Kai Liu (Phoenix, AZ); Rui Tang (Santa Clara, CA); Changhan Hobie Yun (San Diego, CA); Mario Francisco Velez (San Diego, CA); Jonghae Kim (San Diego, CA)
Assignee: QUALCOMM Incorporated
H03H9/542H01P1/20309H01P1/20381H03H3/02H03H9/0542H03H9/0547
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,273,095
App. No.
17/245,901
Granted
Apr 8, 2025
Kind
B2
Abstract

Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.

Claims (19)

1. A method for forming one or more individual bandpass filters on an integrated circuit (IC), the method comprising:

forming a plurality of 3-dimensional (3D) inductors by performing the following:

(a) positioning a first redistribution layer (RDL) in a wafer layer on the integrated circuit (IC);

(b) placing one or more vertical conductive pillars above the wafer layer;

(c) coating a first passivation layer onto the wafer layer;

(d) plating a second redistribution layer (RDL) over the first passivation layer; and

(e) coating a second passivation layer above the second redistribution layer (RDL); and

assembling a plurality of planar resonator chips onto the wafer layer to electrically connect the plurality of planar resonator chips in parallel to the plurality of 3D inductors, wherein the plurality of planar resonator chips includes an intrinsic passband of a first filter transfer function of less than 5% of a center frequency, and wherein a combination of the plurality of planar resonator chips and the plurality of 3D inductors includes an extrinsic passband of a second filter transfer function of greater than 5% of the center frequency.

2. The method of claim 1 , wherein the wafer layer is a molded wafer layer.

3. The method of claim 1 , wherein the one or more vertical conductive pillars are either copper (Cu) pillars or aluminum (Al) pillars.

4. The method of claim 1 , wherein the wafer layer is a high-resistivity silicon (HRS) wafer, a gallium arsenide (GaAs) wafer or a glass wafer.

5. The method of claim 1 , wherein one of the plurality of resonator chips is a bulk acoustic wave (BAW) resonator.

6. The method of claim 1 , further comprising covering the wafer layer with a molding material to form a molded wafer layer.

7. The method of claim 6 , wherein the molding material is an epoxy.

8. The method of claim 6 , further comprising using a transfer-molding process or a compression molding process for covering the wafer layer with the molding material.

9. The method of claim 6 , further comprising back-grinding the molded wafer layer to expose the one or more vertical conductive pillars.

10. The method of claim 6 , further comprising forming an interconnection layer above the second passivation layer.

11. The method of claim 10 , wherein the interconnection layer includes one or more of a solder ball or a conductive pad.

12. The method of claim 10 , further comprising dicing the integrated circuit (IC) to obtain the one or more individual bandpass filters.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2021
From: LIU, KAI; TANG, RUI; YUN, CHANGHAN HOBIE; VELEZ, MARIO FRANCISCO; KIM, JONGHAE
To: QUALCOMM INCORPORATED
Reel/Frame 056100/0915 →
Continuity (2)
Division 16279902 · Feb 19, 2019
Related Publication 20210257989A1 · Aug 19, 2021
References Cited (27)
US 7492242B2 · Carpentier · 2009 [cited by applicant]
US 8471393B2 · Meyer · 2013 [cited by examiner]
US 9048222B2 · Hung · 2015 [cited by examiner]
US 10433425B1 · Liu · 2019 [cited by examiner]
US 10475747B2 · Yu · 2019 [cited by examiner]
US 11335767B2 · Yu · 2022 [cited by examiner]
US 20080135977A1 · Meyer et al. · 2008 [cited by applicant]
US 20090261937A1 · Ko et al. · 2009 [cited by applicant]
US 20140111273A1 · Jou et al. · 2014 [cited by applicant]
US 20140203397A1 · Yen et al. · 2014 [cited by applicant]
US 20140299964A1 · Chen et al. · 2014 [cited by applicant]
US 20150035162A1 · Lan et al. · 2015 [cited by applicant]
US 20150304059A1 · Zuo et al. · 2015 [cited by applicant]
US 20150333401A1 · Maruthamuthu et al. · 2015 [cited by applicant]
US 20170187345A1 · Yun et al. · 2017 [cited by applicant]
US 20180025999A1 · Yu et al. · 2018 [cited by applicant]
US 20180138126A1 · Chen et al. · 2018 [cited by applicant]
US 20190035877A1 · Yu et al. · 2019 [cited by applicant]
US 20200266512A1 · Liu · 2020 [cited by applicant]
Taiwan Search Report—TW109102132—TIPO—Jan. 5, 2024. [cited by applicant]
International Search Report and Written Opinion—PCT/US2020/014047—ISA/EPO—Jun. 29, 2020. [cited by applicant]
Liu K., et al., “Investigation of Integrated Passive Device With Through-silicon via”, Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, IEEE, May 29, 2012 (May 29, 2012), pp. 1833-1839, XP03221084… [cited by applicant]
Bahr B.W.A., “Monolithically Integrated MEMS Resonators and Oscillators in Standard IC Technology”, Massachusetts Institute of Technology, Jun. 2016, pp. 1-255. [cited by applicant]
Chen W-C., et al., “A Generalized CMOS-MEMS Platform for Micromechanical Resonators Monolithically Integrated with Circuits”, Journal of Micromechanics and Microengineering, IOP Publishing, vol. 21, No. 6, May 4, 2011, … [cited by applicant]
Larson L.E., “Integrated Circuit Technology Options for RFIC's-Present Status and Future Directions”, IEEE Journal of Solid-state Circuits, vol. 33, No. 3, Mar. 1998, pp. 387-399. [cited by applicant]
Ondica R., et al., “An Overview of Fully on-Chip Inductors”, Radioengineering, vol. 32, No. 1, Apr. 2023, pp. 11-22. [cited by applicant]
Weigold J.W., et al., “A Merged Process for Thick Single-Crystal Si Resonators and BiCMOS Circuitry”, Journal of Microelectromechanical Systems, vol. 8, No. 3, Sep. 1999, pp. 221-228. [cited by applicant]