Time-interleaved analog to digital converter having asynchronous control
A time-interleaved analog to digital converter includes first and second capacitor array circuits, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a noise shaping signal conversion on the first and second residues to generate a second quantization signal. A turn-on time of the corresponding first transfer circuit is determined based on the coarse conversion corresponding to a first capacitor array circuit and the noise shaping signal conversion corresponding to a second capacitor array circuit to selectively bring forward a start time of the noise shaping signal conversion. The encoder circuit generates a digital output according to the first and the second quantization signals.
1. A time-interleaved analog to digital converter, comprising:
a plurality of capacitor array circuits configured to sequentially sample an input signal and generate a plurality of first residue signals according to a plurality of first quantization signals, wherein the plurality of first quantization signals are generated based on a coarse analog to digital conversion performed based on the input signal;
a plurality of first transfer circuits configured to be turned on according to a plurality of first control signals, in order to sequentially transfer the plurality of first residue signals from the plurality of capacitor array circuits;
a fine converter circuitry configured to perform a noise shaping signal conversion according to a first signal in the plurality of first residue signals and a second signal in a plurality of second residue signals, in order to generate a second quantization signal, wherein a turn-on time of a first one of the plurality of first transfer circuit is determined based on the coarse analog to digital conversion corresponding to a first capacitor array circuit in the plurality of capacitor array circuits and the noise shaping signal conversion corresponding to a second capacitor array circuit in the plurality of capacitor array circuits, in order to selectively bring forward a start time of the noise shaping signal conversion;
a plurality of second transfer circuits configured to sequentially transfer the plurality of second residue signals from the plurality of capacitor array circuits to the fine converter circuitry according to a plurality of second control signals; and
an encoder circuit configured to generate a digital output according to the second quantization signal and a corresponding one of the plurality of first quantization signals.
2. The time-interleaved analog to digital converter of claim 1 , further comprising:
an asynchronous control circuitry configured to generate a corresponding control signal of the plurality of first control signals according to an original control signal, a first detection signal, and a second detection signal,
wherein the first detection signal indicates whether the coarse analog to digital conversion corresponding to the first capacitor array circuit is completed, and the second detection signal indicates whether the noise shaping signal conversion corresponding to the second capacitor array circuit is completed.
3. The time-interleaved analog to digital converter of claim 2 , wherein the original control signal is configured to set a latest start time of the noise shaping signal conversion corresponding to the first capacitor array circuit.
4. The time-interleaved analog to digital converter of claim 2 , wherein the asynchronous control circuitry comprises:
a first logic gate circuit configured to generate a third signal according to the first detection signal and the second detection signal;
a second logic gate circuit configured to generate a fourth signal according to the third signal and the original control signal; and
a flip flop circuit configured to output a voltage to be the corresponding control signal according to the fourth signal, and selectively reset the corresponding control signal according to the second detection signal that corresponds to the first capacitor array circuit,
wherein the first one of the plurality of first transfer circuits is turned on according to the corresponding control signal to transfer the first signal from the first capacitor array circuit to the fine converter circuitry.
5. The time-interleaved analog to digital converter of claim 4 , wherein the first logic gate circuit is an AND gate circuit.
6. The time-interleaved analog to digital converter of claim 4 , wherein the second logic gate circuit is an OR gate circuit.
7. The time-interleaved analog to digital converter of claim 1 , wherein a sampling time for the first capacitor array circuit to sample the input signal is determined based on the noise shaping signal conversion corresponding to the first capacitor array circuit, in order to selectively bring forwards the sampling time for the first capacitor array circuit to sample the input signal.
8. The time-interleaved analog to digital converter of claim 7 , further comprising:
an asynchronous control circuitry configured to generate a third control signal according to an original control signal and a detection signal,
wherein the detection signal indicates whether the noise shaping signal conversion corresponding to the first capacitor array circuit is completed, and the first capacitor array circuit samples the input signal according to the third control signal.
9. The time-interleaved analog to digital converter of claim 8 , wherein the asynchronous control circuitry comprises:
a flip flop circuit configured to output a voltage to a third signal according to the detection signal and selectively reset the third signal according to a reset signal;
a first logic gate circuit configured to generate the third control signal according to the third signal and the original control signal;
an inverter circuit configured to generate a fourth signal according to the original control signal; and
a second logic gate circuit configured to generate the reset signal according to the original control signal and the fourth signal.
10. The time-interleaved analog to digital converter of claim 9 , wherein the first logic gate circuit is an OR gate circuit.
11. The time-interleaved analog to digital converter of claim 9 , wherein the second logic gate circuit is an AND gate circuit.
12. The time-interleaved analog to digital converter of claim 8 , wherein the original control signal is configured to set a latest sampling time for the first capacitor array circuit to sample the input signal.
13. The time-interleaved analog to digital converter of claim 1 , further comprising:
a detector circuitry configured to count according to a specific signal that corresponds to the first capacitor array circuit in the plurality of first quantization signals to sequentially generate a plurality of first flag signals, count according to the second quantization signal to sequentially generate a plurality of second flag signals, generate a first detection signal according to a last one of the plurality of first flag signals, and generate a last one of the plurality of second flag signals to generate a second detection signal,
wherein a turn-on time of the first one of the plurality of first transfer circuits is determined based on the first detection signal and the second detection signal.
14. The time-interleaved analog to digital converter of claim 13 , wherein the first detection signal is a delayed signal of the last one of the plurality of first flag signals, and the second detection signal is a delayed signal of the last one of the plurality of second flag signals.
15. The time-interleaved analog to digital converter of claim 13 , wherein the detector circuitry comprises:
a first counter circuit configured to count according to a first clock signal and the specific signal, in order to sequentially generate the plurality of first flag signals; and
a second counter circuit configured to count according to a second clock signal and the second quantization signal, in order to sequentially generate the plurality of second flag signals.
16. The time-interleaved analog to digital converter of claim 15 , wherein the first counter circuit comprises:
a logic gate circuit configured to generate a valid signal according to the specific signal; and
a plurality flip flop circuits configured to be reset according to the first clock signal and sequentially output a voltage to be the plurality of first flag signals.
17. The time-interleaved analog to digital converter of claim 16 , wherein the logic gate circuit is a XOR gate circuit.
18. The time-interleaved analog to digital converter of claim 15 , wherein the detector circuitry further comprises:
a logic gate circuit configured to generate the second clock signal according to the plurality of first control signals.
19. The time-interleaved analog to digital converter of claim 18 , wherein the logic gate circuit is a NOR gate circuit.
20. The time-interleaved analog to digital converter of claim 1 , further comprising:
a detector circuitry configured to count according to the second quantization signal to generate a plurality of flag signals and output a switching signal according to the plurality of flag signals,
wherein the plurality of capacitor array circuits are further configured to adjust the plurality of second residue signals according to the switching signal.