Control gate structures in three-dimensional memory devices and methods for forming the same
A method includes disposing a layer stack on a substrate, the layer stack including a number of levels. A first control gate structure is formed in a first level of the number of levels by: forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level; removing a remaining portion of the sacrificial layer of the first level to form a first cavity; and disposing a first conductive layer in the first cavity. A second control gate structure is formed in a second level below the first level by: extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening; removing a remaining portion of the sacrificial layer of the second level to form a second cavity; and disposing a second conductive layer in the second cavity.
1. A method for forming a three-dimensional (3D) memory device, comprising:
disposing a layer stack on a substrate, wherein the layer stack includes a plurality of levels;
forming a first control gate structure in a first level of the plurality of levels, wherein forming the first control gate structure further includes:
forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level;
removing a remaining portion of the sacrificial layer of the first level to form a first cavity;
disposing a first dielectric layer in the first cavity; and
disposing a first conductive layer in the first cavity; and
forming a second control gate structure in a second level below the first level, wherein forming the second control gate structure further includes:
extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening;
removing a remaining portion of the sacrificial layer of the second level to form a second cavity;
disposing a second dielectric layer in the second cavity, wherein the first dielectric layer and the second dielectric layer are different materials; and
disposing a second conductive layer in the second cavity.
2. The method of claim 1 , wherein forming the first opening includes exposing a top surface of the dielectric layer of the second level.
3. The method of claim 1 , wherein forming the first opening includes exposing a sidewall surface of the sacrificial layer of the first level.
4. The method of claim 1 , wherein disposing the first and second conductive layers includes disposing first and second conductive materials, wherein material compositions and/or thicknesses of the first and second conductive materials are different.
5. The method of claim 1 , further including disposing a third conductive layer on the first conductive layer and a fourth conductive layer on the second conductive layer.
6. The method of claim 5 , wherein disposing the third and fourth conductive layers includes disposing third and fourth conductive materials, wherein material compositions and/or thicknesses of the third and fourth conductive materials are different.
7. The method of claim 1 , wherein thicknesses of the first and second dielectric layers are different.
8. The method of claim 1 , further including:
forming a channel hole through the layer stack;
disposing a function layer in the channel hole; and
disposing a channel layer in contact with the function layer.
9. The method of claim 8 , wherein forming the first control gate structure further includes:
removing a portion of the function layer through the first cavity and exposing a portion of the channel layer; and
forming the first control gate structure in contact with the exposed portion of the channel layer.
10. The method of claim 8 , wherein:
removing the remaining portion of the sacrificial layer of the second level includes exposing a sidewall portion of the function layer in the second cavity; and
forming the second control gate structure further includes disposing a dielectric material on the exposed sidewall portion of the function layer in the second cavity.
11. A method for forming a three-dimensional (3D) memory device, comprising:
disposing a layer stack on a substrate, wherein the layer stack includes a plurality of levels;
forming a channel structure, wherein forming the channel structure further includes:
forming a channel hole through the layer stack;
disposing a function layer in the channel hole; and
disposing a channel layer in contact with the function layer;
forming a first control gate structure in a first level of the plurality of levels, wherein forming the first control gate structure further includes:
forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level;
removing a remaining portion of the sacrificial layer of the first level;
removing a first portion of the function layer and exposing a portion of the channel layer; and
disposing a first dielectric material on the exposed portion of the channel layer; and
forming a second control gate structure in a second level below the first level, wherein forming the second control gate structure further includes:
extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening;
removing a remaining portion of the sacrificial layer of the second level and exposing a second portion of the function layer; and
disposing a second dielectric material on the exposed second portion of the function layer, wherein the first and second dielectric material are different dielectric materials.
12. The method of claim 11 , further including disposing first and second conductive materials on the first and second dielectric materials, respectively, wherein material compositions and/or thicknesses of the first and second conductive materials are different.
13. The method of claim 12 , further including disposing a third conductive material on the first conductive material and a fourth conductive material on the second conductive material.
14. The method of claim 11 , wherein forming the first and second openings include exposing sidewalls of the sacrificial layer of the first and second levels, respectively.
15. The method of claim 11 , further including etching the layer stack to form a staircase structure.
16. The method of claim 11 , wherein forming the first opening includes exposing a top surface of the dielectric layer of the second level.
17. A three-dimensional (3D) memory device, comprising:
a layer stack disposed on a substrate, wherein the layer stack includes a plurality of levels;
a first control gate structure disposed in a first level of the plurality of levels, including:
a first dielectric layer; and
a first conductive layer in contact with the first dielectric layer; and
a second control gate structure disposed in a second level, including:
a second dielectric layer, wherein dielectric constants of the first and second dielectric layers are different; and
a second conductive layer in contact with the second dielectric layer, wherein material compositions and/or thicknesses of at least portions of the first and second conductive layers are different.
18. The 3D memory device of claim 17 , further including a channel structure extending through the layer stack, wherein the channel structure includes a channel layer at least partially surrounded by a function layer.
19. The 3D memory device of claim 18 , wherein the first control gate structure extends through the function layer and is in contact with the channel layer.
20. The 3D memory device of claim 18 , wherein the second control gate structure is in contact with a sidewall of the function layer.