Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a vertical layer stack located over the alternating stack, the vertical layer stack comprising an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer, wherein the drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures; and

memory stack structures comprising a respective vertical semiconductor channel and a respective memory film vertically extending through the alternating stack, wherein each of the vertical semiconductor channels comprises a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack,

wherein each of the insulating layers and each of the word-line-level electrically conductive layers laterally extend between and contact sidewalls of a pair of dielectric divider structures, and

wherein:

the memory stack structures are arranged in rows that laterally extend along a first horizontal direction; and

each of the drain-select-level isolation structures laterally extends along the first horizontal direction and comprises a laterally alternating sequence of concave vertical sidewall segments and planar vertical sidewall segments.

2. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a vertical layer stack located over the alternating stack, the vertical layer stack comprising an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer, wherein the drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures;

memory stack structures comprising a respective vertical semiconductor channel and a respective memory film vertically extending through the alternating stack, wherein:

each of the vertical semiconductor channels comprises a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack, and

each of the insulating layers and each of the word-line-level electrically conductive layers laterally extend between and contact sidewalls of a pair of dielectric divider structures;

a dielectric cap layer overlying the vertical layer stack, wherein top surfaces of the pair of dielectric divider structures are coplanar with a top surface of the dielectric cap layer; and

drain-select-level insulating spacers contacting a sidewall of a respective one of the pair of dielectric divider structures and a bottom surface of the dielectric cap layer.

3. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a vertical layer stack located over the alternating stack, the vertical layer stack comprising an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer, wherein the drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures; and

memory stack structures comprising a respective vertical semiconductor channel and a respective memory film vertically extending through the alternating stack, wherein each of the vertical semiconductor channels comprises a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack,

wherein each of the drain-select-level semiconductor channel portions is laterally surrounded by a respective gate dielectric having a respective cylindrical shape and contacting the insulating cap layer, a respective one of the drain select electrodes, and the drain-select-level insulating layer, and

wherein each of the drain-select-level semiconductor channel portions contacts a respective cylindrical surface of the insulating cap layer.

4. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a vertical layer stack located over the alternating stack, the vertical layer stack comprising an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer, wherein the drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures; and

memory stack structures comprising a respective vertical semiconductor channel and a respective memory film vertically extending through the alternating stack, wherein each of the vertical semiconductor channels comprises a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack,

wherein the insulating cap layer contacts an annular top surface of each of the connection channel portions.