Fanout module integrating a photonic integrated circuit
A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.
1. A semiconductor package comprising:
a photonic integrated circuit die including a first surface having disposed thereon a photodetector and a plurality of interconnects; and
a semiconductor chip mounted above only a first portion of the first surface, wherein the photodetector is disposed on a second portion of the first surface that is outside of the first portion.
2. The semiconductor package of claim 1 , wherein an optical coupling is disposed above the photodetector of the photonic integrated circuit die.
3. The semiconductor package of claim 1 , further comprising a first encapsulant layer at least partially encasing the semiconductor chip, wherein the first encapsulant layer defines a void through which the photodetector of the photonic integrated circuit die is exposed.
4. The semiconductor package of claim 3 , wherein an optical coupling is disposed within the void.
5. The semiconductor package of claim 1 , further comprising a dielectric layer deposited on the photonic integrated circuit die, the dielectric layer comprising a light transmissible material.
6. The semiconductor package of claim 1 , wherein the photonic integrated circuit die includes one or more through-silicon vias electrically connecting the first surface of the photonic integrated circuit die to a second surface of the photonic integrated circuit die.
7. The semiconductor package of claim 1 , wherein the photonic integrated circuit die and at least one bridge die are embedded in a second encapsulant layer.
8. An apparatus comprising:
a substrate;
a semiconductor package mounted on the substrate, the semiconductor package including:
a photonic integrated circuit die including a first surface having disposed thereon a photodetector and a plurality of interconnects; and
a semiconductor chip mounted above only a first portion of the first surface, wherein the photodetector is disposed on a second portion of the first surface that is outside of the first portion; and
an optical coupling disposed above the photodetector of the photonic integrated circuit die; and
one or more optical fibers coupled to the optical coupling.
9. The apparatus of claim 8 , further comprising a first encapsulant layer at least partially encasing the semiconductor chip, wherein the first encapsulant layer defines a void through which the photodetector of the photonic integrated circuit die is exposed.
10. The apparatus of claim 9 , wherein the optical coupling is disposed within the void.
11. The apparatus of claim 8 , further comprising a dielectric layer deposited on the photonic integrated circuit die, the dielectric layer comprising a light transmissible material.
12. The apparatus of claim 8 , wherein the photonic integrated circuit die includes one or more through-silicon vias electrically connecting the first surface of the photonic integrated circuit die to a second surface of the photonic integrated circuit die.
13. The apparatus of claim 8 , wherein the photonic integrated circuit die and at least one bridge die are embedded in a second encapsulant layer.
14. A method of fabricating a semiconductor package including an embedded photonic integrated circuit, the method comprising:
mounting a photonic integrated circuit die including a first surface having disposed thereon a photodetector and a plurality of interconnects; and
mounting a semiconductor chip above only a first portion of the first surface, wherein the photodetector is disposed on a second portion of the first surface that is outside of the first portion.
15. The method of claim 14 further comprising:
depositing encapsulant material to at least partially encase the semiconductor chip; and
defining a void in the encapsulant material through which the photodetector of the photonic integrated circuit die is exposed.
16. The method of claim 14 further comprising:
mounting an optical coupling above the photodetector of the photonic integrated circuit die.