Verifiable one-time programmable memory device
There is provided a verifiable OTP memory device, the memory device including an MTP memory block and an OTP memory block for storing data, and a memory controller. The memory controller is configured to handle write requests and read requests. Each write request and read request pertains to writing data to, and reading data from, respectively, a requested position in either the MTP memory block or the OTP memory block. The memory controller is configured to, in response to the write requests, write the data to the requested position in either the MTP memory block or the OTP memory block. The memory controller is configured to, in response to the read requests, output data as combined from the requested position in the MTP memory block and the requested position in the OTP memory block, regardless if the read requests are for the MTP memory block or the OTP memory block.
1. A verifiable one-time programmable, OTP, memory device, the memory device comprising a multiple-time programmable, MTP, memory block and an OTP memory block for storing data, and a memory controller, wherein the memory controller is configured to:
handle write requests and read requests, wherein each write request and read request pertains to writing data to, and reading data from, respectively, a requested position in either the MTP memory block or the OTP memory block,
in response to the write requests, write the data to the requested position in either the MTP memory block or the OTP memory block, and
in response to the read requests, output data as combined from the requested position in the MTP memory block and the requested position in the OTP memory block, regardless if the read requests are for the MTP memory block or the OTP memory block.
2. The memory device according to claim 1 , wherein the memory device is configured to permanently disable writing of data to the MTP memory block.
3. The memory device according to claim 1 , wherein writing of data to the MTP memory block is permanently disabled by a fuse in the memory device being blown.
4. The memory device according to claim 1 , wherein the memory device is configured to permanently reject read requests for the MTP memory block.
5. The memory device according to claim 1 , wherein when a control bit in the memory device is set, data read from the MTP memory block is set to zero before being combined with the data read from the OTP memory block.
6. The memory device according to claim 1 , wherein when a fuse in the memory device is blown, data read from the MTP memory block is set to zero before being combined with the data read from the OTP memory block.
7. The memory device according to claim 1 , wherein the memory device is configured to permanently disable writing of data to the OTP memory block.
8. The memory device according to claim 1 , wherein any writing of data to the OTP memory block involves first writing the data to the MTP memory block, where the written data defines a state for the MTP memory block, and then copying the state of the MTP memory block to the OTP memory block.
9. The memory device according to claim 1 , wherein the MTP memory block and the OTP memory block share a common address space, and whether the requested position in the MTP memory block or in the OTP memory block is defined by an indicator provided in the write requests and the read requests, respectively.
10. The memory device according to claim 9 , wherein the indicator is a single bit.
11. The memory device according to claim 1 , wherein the memory device further comprises a cache, and wherein the memory controller is configured to write the data to, and read the data from, respectively, the MTP memory block and the OTP memory block via the cache.
12. The memory device according to claim 1 , wherein the memory device comprises at least two MTP memory blocks and as many OTP memory blocks as MTP memory blocks, where each MTP memory block forms a pair with a respective one of the OTP memory blocks, and where the memory controller is configured to handle write requests and read requests individually for each such pair of one MTP memory block and one OTP memory block.
13. The memory device according to claim 1 , wherein each write request pertains to writing one bit of data to the requested position.
14. The memory device according to claim 1 , wherein each read request pertains to reading one bit of data from the requested position.
15. The memory device according to claim 1 , wherein the memory controller is configured to combine the read data by implementing a logic OR operation between the data as read from the MTP memory block and the data as read from the OTP memory block.
16. A method for handling a write request in a verifiable one-time programmable, OTP, memory device according to claim 1 , the method comprising:
receiving a write request for writing data to a requested position in either the MTP memory block or the OTP memory block; and
writing the data to the requested position.
17. A method for handling a read request in a verifiable one-time programmable, OTP, memory device according to claim 1 , the method comprising:
receiving a read request for reading data from a requested position in either the MTP memory block or the OTP memory block;
combining data from the requested position in the MTP memory block with data from the requested position in the OTP memory block; and
outputting the combined data.