Block family error avoidance bin designs addressing error correction decoder throughput specifications
A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
maintaining a set of bins, each bin of the set of bins defining a respective grouping of blocks of memory cells in the memory array based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, wherein the set of bins comprises a first bin and a second bin having an associated read window overlap between a first read window defined for the first bin and a second read window defined for the second bin, and wherein the first read window and the second read window correspond to respective valley margins between respective pairs of adjacent threshold voltage distributions;
receiving a request to perform a read operation addressing a block of the grouping of blocks of memory cells assigned to the first bin; and
causing the read operation addressing the block to be performed based on the respective read level offset assigned to the first bin.
2. The memory device of claim 1 , wherein maintaining the set of bins comprises receiving a predefined set of bins, and storing the predefined set of bins as the set of bins.
3. The memory device of claim 1 , wherein maintaining the set of bins comprises updating the set of bins by performing a scan operation to determine whether to reassign the block from the first bin to another bin of the set of bins.
4. The memory device of claim 1 , wherein causing the read operation addressing the block to be performed comprises identifying the first bin to which the block is assigned, and selecting the respective read level offset assigned to the first bin as a selected read level offset.
5. The memory device of claim 4 , wherein causing the read operation addressing the block to be performed further comprises performing the read operation addressing the block using the selected read level offset.
6. The memory device of claim 1 , wherein the first bin has a first width and the second bin has a second width different from the first width.
7. The memory device of claim 6 , wherein the first bin has a lower bin index than the second bin, and wherein the first width is greater than the second width.
8. A method comprising:
maintaining, by a processing device, a set of bins, each bin of the set of bins defining a respective grouping of blocks of memory cells in a memory array based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, wherein the set of bins comprises a first bin and a second bin having an associated read window overlap between a first read window defined for the first bin and a second read window defined for the second bin, and wherein the first read window and the second read window correspond to respective valley margins between respective pairs of adjacent threshold voltage distributions;
receiving, by the processing device, a request to perform a read operation addressing a block of the grouping of blocks of memory cells assigned to the first bin; and
causing, by the processing device, the read operation addressing the block to be performed based on the respective read level offset assigned to the first bin.
9. The method of claim 8 , wherein maintaining the set of bins comprises receiving a predefined set of bins, and storing the predefined set of bins as the set of bins.
10. The method of claim 8 , wherein maintaining the set of bins comprises updating the set of bins by performing a scan operation to determine whether to reassign the block from the first bin to another bin of the set of bins.
11. The method of claim 8 , wherein causing the read operation addressing the block to be performed comprises identifying the first bin to which the block is assigned, and selecting the respective read level offset assigned to the first bin as a selected read level offset.
12. The method of claim 11 , wherein causing the read operation addressing the block to be performed further comprises performing the read operation addressing the block using the selected read level offset.
13. The method of claim 8 , wherein the first bin has a first width and the second bin has a second width different from the first width.
14. The method of claim 13 , wherein the first bin has a lower bin index than the second bin, and wherein the first width is greater than the second width.
15. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
receiving a request to perform a read operation addressing a block of memory cells in the memory array;
in response to receiving the request, identifying a first bin of a set of bins to which the block is assigned, the first bin defining a first grouping of blocks of memory cells comprising the block based on elapsed time since programming, wherein the first bin is assigned a read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, wherein the set of bins further comprises a second bin having an associated read window overlap between a first read window defined for the first bin and a second read window defined for the second bin, and wherein the first read window and the second read window correspond to respective valley margins between respective pairs of adjacent threshold voltage distributions; and
selecting the read level offset to perform the read operation address the block.
16. The memory device of claim 15 , wherein the operations further comprise receiving the set of bins comprising the first bin and the second bin as a predefined set of bins, and storing the predefined set of bins.
17. The memory device of claim 16 , wherein the operations further comprise updating the set of bins by performing a scan operation to determine whether to reassign the block from the first bin to another bin of the set of bins.
18. The memory device of claim 15 , wherein the operations further comprise performing the read operation addressing the block using the read level offset.
19. The memory device of claim 15 , wherein the first bin has a first width and the second bin has a second width different from the first width.
20. The memory device of claim 19 , wherein the first bin has a lower bin index than the second bin, and wherein the first width is greater than the second width.