Droop detection and control of digital frequency-locked loop
An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
1. An integrated circuit comprising:
a power supply monitor operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage;
a clock generator operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word; and
a divider responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
2. The integrated circuit of claim 1 , wherein the power supply monitor comprises:
a fast droop detector.
3. The integrated circuit of claim 1 , wherein the clock generator comprises:
a digital frequency locked loop.
4. The integrated circuit of claim 1 , wherein:
the power supply monitor has an input for receiving a reference signal and an output for providing the frequency control word in response to the reference signal; and
the clock generator adjusts the frequency of the first clock signal according to the value of the frequency control word.
5. The integrated circuit of claim 4 , wherein the clock generator adjusts the frequency of the first clock signal according to a native adaptive stretch having a finite slope that is programmable using at least one parameter.
6. The integrated circuit of claim 5 , wherein the at least one parameter comprises one or more of: an initial stretch, a maximum stretch, a decremental stretch, a final stretch, and a step time.
7. The integrated circuit of claim 1 , wherein:
the divider is further responsive to a deep sleep signal to divide the frequency of the first clock signal by the divide value to provide the second clock signal.
8. The integrated circuit of claim 1 , wherein the clock generator further comprising:
a finite state machine for providing the frequency control word selectively in response to a plurality of control mechanisms, and provides a new frequency control word in response to a largest change indicated by the plurality of control mechanisms.
9. An integrated circuit comprising:
a power supply monitor having an input for receiving a power supply voltage, and an output for providing a trigger signal in response to the power supply voltage dropping below a threshold voltage;
a clock generator having an output for providing a first clock signal having a frequency dependent on a value of a frequency control word, and providing a native slope for changing the frequency of the first clock signal over time in response to a change in the frequency control word; and
a divider having an input for receiving the first clock signal and responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
10. The integrated circuit of claim 9 , wherein the power supply monitor comprises:
a fast droop detector.
11. The integrated circuit of claim 9 , wherein the clock generator comprises:
a digital frequency locked loop.
12. The integrated circuit of claim 9 , wherein:
the power supply monitor has an input for receiving a reference signal and an output for providing the frequency control word in response to the reference signal; and
the clock generator adjusts the frequency of the first clock signal according to the value of the frequency control word.
13. The integrated circuit of claim 12 , wherein the clock generator adjusts the frequency of the first clock signal according to a native adaptive stretch having a finite slope that is programmable using at least one parameter.
14. The integrated circuit of claim 13 , wherein the at least one parameter comprises one or more of: an initial stretch, a maximum stretch, a decremental stretch, a final stretch, and a step time.
15. The integrated circuit of claim 9 , wherein:
the divider is further responsive to a deep sleep signal to divide the frequency of the first clock signal by the divide value to provide the second clock signal.
16. The integrated circuit of claim 9 , wherein the clock generator further comprising:
a finite state machine for providing the frequency control word selectively in response to a plurality of control mechanisms, and provides a new frequency control word in response to a largest change indicated by the plurality of control mechanisms.
17. A method comprising:
determining whether a power supply voltage is below a threshold voltage;
if the power supply voltage is below the threshold voltage:
activating a trigger signal; and
dividing a first clock signal by a divide value to provide a second clock signal;
if the power supply voltage is not below the threshold voltage:
selectively stretching and unstretching the first clock signal according to at least one control mechanism; and
repeating determining whether the power supply voltage is below the threshold voltage.
18. The method of claim 17 , further comprising:
if the power supply voltage is below the threshold voltage:
selectively stretching and unstretching the first clock signal according to the at least one control mechanism after the dividing;
determining whether a hysteresis period has ended and the power supply voltage is above the threshold voltage; and
repeating selectively stretching and unstretching until the hysteresis period has ended and the power supply voltage is above the threshold voltage.
19. The method of claim 18 , further comprising:
in response to the hysteresis period ending and the power supply voltage being above the threshold voltage:
stopping dividing the first clock signal by the divide value to provide the second clock signal; and
resuming determining whether the power supply voltage is below the threshold voltage.
20. The method of claim 18 , wherein selectively stretching and unstretching the first clock signal according to the at least one control mechanism after the dividing further comprises:
selectively stretching and unstretching the first clock signal according to a plurality of control mechanisms after the dividing.