Three-dimensional memory devices with supporting structure for staircase region and spacer structure for contact structure and methods for forming the same
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.
1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers and comprising a staircase region in a plan view;
a semiconductor layer in contact with the memory stack;
a supporting structure overlapping and arranged within the staircase region of the memory stack to be aligned with the memory stack in a vertical direction of the plan view; and
a source contact structure at a side of the semiconductor layer opposite to the memory stack and in contact with the semiconductor layer,
wherein:
the supporting structure comprises a material other than a material of the semiconductor layer;
a spacer structure is arranged outside the memory stack;
in a lateral direction perpendicular to the vertical direction, the supporting structure is sandwiched within the semiconductor layer without extending to a core array region adjacent to the staircase region;
a contact structure extending vertically and surrounded by the spacer structure;
a stop layer extends, at the side of the semiconductor layer opposite to the memory stack, in the lateral direction, and the supporting structure and the spacer structure terminate on the stop layer; and
the source contact structure penetrates the stop layer to electrically couple with a channel structure through the semiconductor layer.
2. The 3D memory device of claim 1 , wherein the spacer structure has a trench structure surrounding part of the semiconductor layer, wherein the part of the semiconductor layer is in contact with the contact structure and is insulated from a rest of the semiconductor layer by the spacer structure.
3. The 3D memory device of claim 1 , wherein the spacer structure has a well structure, wherein a shape of the well structure is different from a shape of the contact structure in the plan view.
4. The 3D memory device of claim 1 , wherein the spacer structure comprises a dielectric material.
5. The 3D memory device of claim 1 , wherein the supporting structure and the spacer structure comprise a same dielectric material.
6. The 3D memory device of claim 5 , wherein the same dielectric material is tetraethyl orthosilicate (TEOS).
7. The 3D memory device of claim 1 , further comprising a first slit structure extending vertically and laterally and dividing the memory stack into a plurality of memory blocks.
8. The 3D memory device of claim 7 , further comprising a second slit structure extending vertically and laterally and dividing each memory stack into a plurality of memory fingers.
9. The 3D memory device of claim 8 , wherein the second slit structure stops in the supporting structure, wherein each memory block overlaps with a respective supporting structure.
10. The 3D memory device of claim 8 , wherein the second slit structure extends vertically into the semiconductor layer and is configured to divide the supporting structure into a plurality of sub-supporting structures, wherein each memory finger overlaps with one of the sub-supporting structures.
11. The 3D memory device of claim 10 , wherein each of the sub-supporting structures comprises a trench structure surrounding part of the semiconductor layer.
12. The 3D memory device of claim 10 , wherein each of the sub-supporting structures comprises a well structure filled with the material different than the material of the semiconductor layer.
13. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view;
a semiconductor layer in contact with the memory stack;
a supporting structure overlapping and arranged within the staircase region of the memory stack to be aligned with the staircase region in a vertical direction of the plan view, wherein:
the supporting structure comprises a material other than a material of the semiconductor layer, and an upper surface of the supporting structure is flush with an upper surface of the semiconductor layer; and
in a lateral direction perpendicular to the vertical direction, the supporting structure is sandwiched within the semiconductor layer;
a spacer structure outside the memory stack;
a source contact structure at a side of the semiconductor layer opposite to the memory stack and in contact with the semiconductor layer;
a channel structure in the core array region of the memory stack and into the semiconductor layer, comprising a semiconductor channel, wherein a lower portion of the semiconductor channel is surrounded by and in direct contact with the semiconductor layer; and
a contact structure extending vertically and surrounded by the spacer structure,
wherein:
a stop layer extends, at the side of the semiconductor layer opposite to the memory stack, in the lateral direction, and the supporting structure and the spacer structure terminate on the stop layer; and
the source contact structure penetrates the stop layer to electrically couple with the channel structure through the semiconductor layer.
14. The 3D memory device of claim 13 , wherein the spacer structure has a trench structure surrounding part of the semiconductor layer, wherein the part of the semiconductor layer is in contact with the contact structure and is insulated from a rest of the semiconductor layer by the spacer structure.
15. The 3D memory device of claim 13 , wherein the spacer structure has a well structure, wherein a shape of the well structure is different from a shape of the contact structure in the plan view.
16. The 3D memory device of claim 13 , further comprising a first slit structure extending vertically and laterally and dividing the memory stack into a plurality of memory blocks.
17. The 3D memory device of claim 16 , further comprising a second slit structure extending vertically and laterally and dividing each memory stack into a plurality of memory fingers.
18. The 3D memory device of claim 17 , wherein the second slit structure stops in the supporting structure, wherein each memory block overlaps with a respective supporting structure.
19. The 3D memory device of claim 17 , wherein the second slit structure extends vertically into the semiconductor layer and is configured to divide the supporting structure into a plurality of sub-supporting structures, wherein each memory finger overlaps with one sub-supporting structure.