Semiconductor structure and manufacturing method thereof
The present disclosure relates to a semiconductor structure and a manufacturing method thereof, including: a substrate; a plurality of transistors, arranged based on a first preset pattern; a plurality of transistor contact structures, corresponding to the transistors, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of which are arranged based on the shape of a regular hexagon; a plurality of memory cells, corresponding to the transistor contact structures, the memory cells are arranged based on the shape of a regular hexagon; and a plurality of memory contact structures, corresponding to the memory cells, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of which are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern.
1. A semiconductor structure, comprising:
a substrate, having a first surface;
a plurality of transistors, located on the first surface and arranged based on a first preset pattern;
a plurality of transistor contact structures, corresponding to the transistors in a one-to-one manner, wherein bottom portions of the transistor contact structures are in contact with the transistors respectively, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of the transistor contact structures are arranged based on the shape of a regular hexagon;
a plurality of memory cells, corresponding to the transistor contact structures in a one-to-one manner, wherein bottom portions of the memory cells are in contact with the top portions of the transistor contact structures respectively, and the memory cells are arranged based on the shape of a regular hexagon and located at vertex positions and a central position of the regular hexagon; and
a plurality of memory contact structures, corresponding to the memory cells in a one-to-one manner, wherein bottom portions of the memory contact structures are in contact with top portions of the memory cells respectively, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of the memory contact structures are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern;
wherein the bottom portion of the transistor contact structure is arranged opposite to the top portion of the transistor contact structure, and the bottom portion of the memory contact structure is arranged opposite to the top portion of the memory contact structure.
2. The semiconductor structure according to claim 1 , wherein the first preset pattern comprises a regular hexagon, and the transistors are located at vertex positions and a central position of the regular hexagon.
3. The semiconductor structure according to claim 2 , wherein an area of the top portion of the transistor contact structure is equal to that of the bottom portion of the transistor contact structure.
4. The semiconductor structure according to claim 2 , wherein the second preset pattern comprises an arrangement array with a plurality of rows and columns.
5. The semiconductor structure according to claim 4 , wherein an area of the bottom portion of the memory contact structure is larger than that of the top portion of the memory contact structure.
6. The semiconductor structure according to claim 1 , wherein the first preset pattern comprises an arrangement array with a plurality of rows and columns.
7. The semiconductor structure according to claim 6 , wherein an area of the top portion of the transistor contact structure is smaller than that of the bottom portion of the transistor contact structure.
8. The semiconductor structure according to claim 6 , wherein the second preset pattern comprises a regular hexagon, and the memory contact structures are located at vertex positions and a central position of the regular hexagon.
9. The semiconductor structure according to claim 8 , wherein an area of the top portion of the memory contact structure is equal to that of the top portion of the memory contact structure.
10. The semiconductor structure according to claim 1 , wherein the transistor contact structures each comprise:
a first lead-out structure, wherein a bottom portion of the first lead-out structure is the bottom portion of the transistor contact structure; and
a second lead-out structure, wherein a bottom portion of the second lead-out structure is in contact with a top portion of the first lead-out structure, and a top portion of the second lead-out structure is the top portion of the transistor contact structure;
wherein the bottom portion of the first lead-out structure is arranged opposite to the top portion of the first lead-out structure, and the bottom portion of the second lead-out structure is arranged opposite to the top portion of the second lead-out structure.
11. The semiconductor structure according to claim 10 , wherein an area of the bottom portion of the second lead-out structure is larger than or equal to that of the top portion of the first lead-out structure.
12. The semiconductor structure according to claim 1 , the semiconductor structure further comprises:
a word line structure, in contact with a gate region of the transistor; and
a source line structure, in contact with a source region of the transistor;
wherein a drain region of the transistor is in contact with the bottom portion of the transistor contact structure.
13. The semiconductor structure according to claim 1 , wherein the memory cell comprises a ferroelectric memory cell, a magnetoresistive memory cell, a resistance change memory cell, or a phase change memory cell.
14. The semiconductor structure according to claim 4 , the semiconductor structure further comprises:
a plurality of bit line structures, wherein any one of the bit line structures is in contact with the top portion of the memory contact structure in a same column.
15. The semiconductor structure according to claim 8 , wherein the semiconductor structure further comprises:
a plurality of bit line structures, wherein any one of the bit line structures is in contact with the top portions of the memory contact structures in two neighboring columns.
16. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, wherein the substrate has a first surface;
forming a plurality of transistors on the first surface, wherein the transistors are arranged based on a first preset pattern;
forming transistor contact structures on the transistors respectively, wherein bottom portions of the transistor contact structures are in contact with the transistors respectively, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of the transistor contact structures are arranged based on the shape of a regular hexagon;
forming memory cells on the top portions of the transistor contact structures respectively, wherein the memory cells are arranged based on the shape of a regular hexagon and located at vertex positions and a central position of the regular hexagon; and
forming memory contact structures on top portions of the memory cells respectively, wherein bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, the top portions of the memory contact structures are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern;
wherein the bottom portion of the transistor contact structure is arranged opposite to the top portion of the transistor contact structure, and the bottom portion of the memory contact structure is arranged opposite to the top portion of the memory contact structure.
17. The manufacturing method according to claim 16 , wherein the first preset pattern comprises a regular hexagon, and the transistors are located at vertex positions and a central position of the regular hexagon; and
an area of the top portion of the transistor contact structure is equal to that of the bottom portion of the transistor contact structure.
18. The manufacturing method according to claim 17 , wherein the second preset pattern comprises an arrangement array with a plurality of rows and columns; and
an area of the bottom portion of the memory contact structure is larger than that of the top portion of the memory contact structure.
19. The manufacturing method according to claim 16 , wherein the first preset pattern comprises an arrangement array with a plurality of rows and columns; and
an area of the top portion of the transistor contact structure is smaller than that of the bottom portion of the transistor contact structure.
20. The manufacturing method according to claim 19 , wherein the second preset pattern comprises a regular hexagon, and the memory contact structures are located at vertex positions and a central position of the regular hexagon.