Techniques for memory access in a reduced power state
Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.
1. An apparatus, comprising:
a memory controller comprising circuitry for a memory manager to:
identify a low power mode block and a non-low power mode block in a set of functional blocks;
map the low power mode block to a first memory channel associated with a first address of a memory;
map the non-low power mode block to a second memory channel associated with a second address of the memory that is different from the first address of the memory; and
processor circuitry operably coupled to the circuitry for the memory manager, the processor circuitry comprising a processor core, the processor circuitry to disable the second memory channel to establish a low-power communication pipeline between the processor core and the memory via the first memory channel.
2. The apparatus of claim 1 , the processor circuitry to establish a low power communication pipeline between a processor core and the memory via the first memory channel.
3. The apparatus of claim 1 , the processor circuitry to establish a non-low power communication pipeline between a processor core and the memory via the second memory channel.
4. The apparatus of claim 1 , the processor circuitry to receive an indication of a transition from a first power state to a second power state, wherein the second power state is a lower power state than the first power state, to initiate establishment of a low power communication pipeline between a processor core and the memory via the first memory channel.
5. The apparatus of claim 1 , the processor circuitry to set a memory module associated with the second memory channel to a self-refresh mode to disable the second memory channel.
6. The apparatus of claim 1 , the processor circuitry to utilize power gating on a memory module associated with the second memory channel to disable the second memory channel.
7. The apparatus of claim 1 , comprising the memory operably coupled to the circuitry for the memory manager via a memory bus, the memory comprising a first memory portion and a second memory portion, the first memory portion comprising main memory and the second memory portion comprising secondary memory.
8. The apparatus of claim 1 , comprising a chipset operably coupled to the circuitry for the memory manager via a second interconnect, the chipset comprising the set of functional blocks.
9. At least one non-transitory computer-readable medium comprising a set of instructions that, in response to being executed by a circuit, cause the circuit to:
identify a low power mode block and a non-low power mode block in a set of functional blocks;
map the low power mode block to a first memory channel associated with a first address of a memory;
map the non-low power mode block to a second memory channel associated with a second address of the memory that is different from the first address of the memory; and
disable the second memory channel to establish a low-power communication pipeline between a processor core and the memory via the first memory channel.
10. The at least one non-transitory computer-readable medium of claim 9 , comprising instructions that, in response to being executed by the circuit cause the circuit to establish a low power communication pipeline between a processor core and the memory via the first memory channel.
11. The at least one non-transitory computer-readable medium of claim 9 , comprising instructions that, in response to being executed by the circuit cause the circuit to establish a non-low power communication pipeline between a processor core and the memory via the second memory channel.
12. The at least one non-transitory computer-readable medium of claim 9 , comprising instructions that, in response to being executed by the circuit cause the circuit to:
set a memory module associated with the second memory channel to a self-refresh mode to disable the second memory channel; or
utilize power gating on a memory module associated with the second memory channel to disable the second memory channel.
13. A method, comprising:
identifying a low power mode block and a non-low power mode block in a set of functional blocks;
mapping the low power mode block to a first memory channel associated with a first address of a memory; and
mapping the non-low power mode block to a second memory channel associated with a second address of the memory that is different from the first address of the memory; and
disabling the second memory channel to establish a low-power communication pipeline between a processor core and the memory via the first memory channel.
14. The method of claim 13 , comprising establishing a low power communication pipeline between a processor core and the memory via the first memory channel.
15. The method of claim 13 , comprising establishing a non-low power communication pipeline between a processor core and the memory via the second memory channel.
16. The method of claim 13 , comprising:
setting a memory module associated with the second memory channel to a self-refresh mode to disable the second memory channel; or
utilizing power gating on a memory module associated with the second memory channel to disable the second memory channel.