Test circuit of semiconductor apparatus and test system including the same
A test circuit of a semiconductor apparatus includes a first resistor, a second resistor and a feed-back loop circuit. The first resistor is coupled between a pad and a test element. The second resistor is coupled to the first resistor in a parallel manner. The feed-back loop circuit is configured to feed a result back to the second resistor, the result being one of comparing a first voltage and a second voltage with each other, the first voltage and the second voltage being applied respectively to the first resistor and the second resistor.
1. A test circuit of a semiconductor apparatus, the test circuit comprising:
a plurality of test-target elements;
a first signal path configured to provide a voltage applied to a first pad, to a first test-target element selected from among the plurality of test-target elements;
a current dividing circuit configured to divide a current through a second signal path and a third signal path, the current being caused by a voltage applied to a second pad; and
a feed-back loop circuit configured to feed a result back by using the third signal path, the result being obtained by comparing a first voltage corresponding to the second signal path and a second voltage corresponding to the third signal path,
wherein the first signal path includes a demultiplexer configured to couple, according to a control signal, the first pad to one of the plurality of test-target elements.
2. The test circuit of claim 1 , wherein the current dividing circuit includes first and second resistor coupled in parallel to the second pad,
wherein the second resistor has a resistance value which is reduced by a predetermined ratio from a resistance value of the first resistor.
3. The test circuit of claim 2 , further comprising a demultiplexer configured to couple, according to a control signal, the first resistor to one of the plurality of test-target elements,
wherein the demultiplexer and the first resistor are included in the second signal path.
4. The test circuit of claim 2 , wherein the feed-back loop circuit includes:
a differential amplifier configured to compare the first voltage and the second voltage with each other; and
a transistor coupled between the second resistor and a ground and configured to operate according to an output of the differential amplifier.
5. The test circuit of claim 4 , wherein the third signal path includes:
the second resistor; and
the transistor.
6. A test circuit of a semiconductor apparatus, the test circuit comprising:
a plurality of test-target elements;
a first demultiplexer configured to provide a voltage which is applied to a first pad, to a first node of a first test-target element selected from among the plurality of test-target elements;
a first resistor coupled to a second pad;
a second demultiplexer configured to provide a voltage which is applied to the first resistor, to a second node of the first test-target element;
a second resistor coupled to the second pad in parallel with the first resistor; and
a feed-back loop circuit configured to feed a result back to the second resistor, the result being obtained by comparing a first voltage applied to the first resistor and a second voltage applied to the second resistor.
7. The test circuit of claim 6 , wherein the second resistor has a resistance value which is reduced by a predetermined ratio from a resistance value of the first resistor.
8. The test circuit of claim 6 , wherein the feed-back loop circuit includes:
a differential amplifier configured to compare the first voltage and the second voltage with each other; and
a transistor coupled between the second resistor and a ground and configured to operate according to an output of the differential amplifier.
9. A test system comprising:
a test equipment configured to perform a test by applying a voltage through a first pad and by monitoring a current that flows through a second pad according to the voltage;
a semiconductor die to be tested, including a test circuit;
wherein the test circuit comprises:
a first resistor coupled between a plurality of test-target elements and the second pad; and
a second resistor coupled to the second pad in parallel with the first resistor,
wherein the test circuit is configured to feed a result back by using the second resistor, the result being obtained by comparing a first voltage applied to the first resistor and a second voltage applied to the second resistor.
10. The test system of claim 9 , wherein the test circuit further comprises:
a first demultiplexer configured to provide a voltage which is applied to the first pad, to a first node of a first test-target element selected from among the plurality of test-target elements;
a second demultiplexer configured to provide a voltage which is applied to the first resistor, to a second node of the first test-target element; and
a feed-back loop circuit configured to feed the result back by using the second resistor.
11. The test system of claim 10 , wherein the feed-back loop circuit includes:
a differential amplifier configured to compare the first voltage and the second voltage with each other; and
a transistor coupled between the second resistor and a ground and configured to operate according to an output of the differential amplifier.
12. The test system of claim 9 , wherein the second resistor has a resistance value which is reduced by a predetermined ratio from a resistance value of the first resistor.