Manufacturing method of semiconductor device
View Patent ↗A method includes forming a first multilayer interconnection structure over a carrier substrate. A first interlayer dielectric (ILD) layer is deposited over the first multilayer interconnection structure. A first source/drain contact is formed in the first ILD layer. After forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ILD layer. The semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. A gate structure is formed across the semiconductor fin. The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.
1. A method comprising:
forming a first multilayer interconnection structure over a carrier substrate;
depositing a substrate over the first multilayer interconnection structure;
forming a first source/drain contact in the substrate and electrically connected to the first multilayer interconnection structure;
patterning the substrate to form a semiconductive fin such that the first source/drain contact is embedded in the semiconductive fin;
forming a gate structure over the semiconductive fin;
patterning the semiconductive fin to form a recess in the semiconductive fin such that the recess exposes a top surface of the first source/drain contact; and
forming a source/drain epitaxial structure in the recess and in contact with the first source/drain contact.
2. The method of claim 1 , further comprising forming a semiconductive stacked structure over the substrate after forming the first source/drain contact and prior to pattering the substrate.
3. The method of claim 2 , wherein forming the semiconductive stacked structure comprises:
forming a first semiconductive layer over the substrate and in contact with the first source/drain contact; and
forming a second semiconductive layer over the first semiconductive layer, wherein the first and second semiconductive layers comprise different materials.
4. The method of claim 3 , further comprising pattering the semiconductive stacked structure to form a fin structure covering the first source/drain contact.
5. The method of claim 1 , further comprising forming an isolation structure surrounding the semiconductive fin, such that a top surface of the isolation structure is lower than a top surface of the first source/drain contact.
6. The method of claim 1 , further comprising forming a second multilayer interconnection structure over the gate structure and the source/drain epitaxial structure.
7. The method of claim 6 , wherein forming the second multilayer interconnection structure is such that both a metal line of the second multilayer interconnection structure and a metal line of the first multilayer interconnection structure taper downward.
8. A method comprising:
forming a first interlayer dielectric (ILD) layer over a first multilayer interconnection structure on a carrier substrate;
forming a substrate over the first ILD layer;
forming a first source/drain contact through the substrate and the first ILD layer to the first multilayer interconnection structure; and
after the first source/drain contact is formed, patterning the substrate to form a semiconductive fin, wherein the first source/drain contact is embedded in the semiconductive fin and the first ILD layer.
9. The method of claim 8 , further comprising:
forming a gate structure over the semiconductive fin.
10. The method of claim 8 , further comprising:
forming a first source/drain epitaxial structure in contact with a top surface and a sidewall of the first source/drain contact.
11. The method of claim 10 , wherein the first source/drain epitaxial structure extends between the first source/drain contact and the semiconductive fin.
12. The method of claim 10 , further comprising:
forming a second source/drain contact over the first source/drain epitaxial structure.
13. The method of claim 10 , further comprising:
forming a second source/drain epitaxial structure in the semiconductive fin and spaced apart from the first source/drain epitaxial structure.
14. The method of claim 8 , further comprising:
forming an isolation structure surrounding the semiconductive fin, such that a top surface of the isolation structure is lower than a top surface of the first source/drain contact.
15. A method, comprising:
forming a first multilayer interconnection structure over a carrier substrate;
forming a substrate over the first multilayer interconnection structure
forming a first source/drain contact embedded in the substrate;
patterning the substrate to form semiconductive fins, wherein the first source/drain contact is embedded in one of the semiconductive fins; and
forming isolation structures between the semiconductive fins, wherein the first source/drain contact protrudes from the isolation structures.
16. The method of claim 15 , wherein a bottom surface of the first source/drain contact is lower than bottom surfaces of the semiconductive fins.
17. The method of claim 15 , further comprising:
forming a source/drain epitaxial structure in contact with top surface and sidewall of the first source/drain contact.
18. The method of claim 17 , further comprising:
forming a second source/drain contact over the source/drain epitaxial structure.
19. The method of claim 17 , further comprising:
forming a second multilayer interconnection structure over the source/drain epitaxial structure.
20. The method of claim 19 , forming the second multilayer interconnection structure is such that both a metal line of the second multilayer interconnection structure and a metal line of the first multilayer interconnection structure taper downward.