IP Library › Granted Patent US 12,284,456
Granted Patent B2
US 12,284,456 · App. 18/259,334 · Granted Apr 22, 2025

Imaging device and distance measurement system

Inventor: Keishi Kumata (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N25/772H04N23/56H04N23/667H04N25/705H04N25/779H04N25/7795H04N25/78H04N25/767
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Quick Facts
Patent No.
US 12,284,456
App. No.
18/259,334
Granted
Apr 22, 2025
Kind
B2
Abstract

Provided is an imaging device capable of suppressing a decrease in a frame rate while improving charge transfer efficiency. An imaging device according to an embodiment of the present disclosure includes: a photoelectric conversion element; a signal converter that is boosted when charge transferred from the photoelectric conversion element is converted into a pixel signal; a selection transistor that interrupts a signal line of the pixel signal during a boosting period of the signal converter; a comparator including a non-inverting input terminal to which the pixel signal is input via the selection transistor, an inverting input terminal to which a ramp signal is input, and an output terminal which outputs a comparison result between the pixel signal and the ramp signal; and a correction circuit that holds a potential of the non-inverting input terminal in the boosting period at a potential of the non-inverting input terminal before the boosting period.

Claims (45)

1. An imaging device, comprising:

a photoelectric conversion element;

a signal converter that is boosted when charge transferred from the photoelectric conversion element is converted into a pixel signal;

a selection transistor that interrupts a signal line of the pixel signal during a boosting period of the signal converter;

a comparator including a non-inverting input terminal to which the pixel signal is input via the selection transistor, an inverting input terminal to which a ramp signal is input, and an output terminal which outputs a comparison result between the pixel signal and the ramp signal; and

a correction circuit that holds a potential of the non-inverting input terminal in the boosting period at a potential of the non-inverting input terminal before the boosting period.

2. The imaging device according to claim 1 , wherein

the correction circuit includes:

a first transistor arranged between the selection transistor and the non-inverting input terminal;

a second transistor paired with the first transistor;

a first switch arranged between a gate of the first transistor and a gate of the second transistor;

a second switch arranged between a source of the first transistor and a source of the second transistor; and

a capacitor connected to the gate of the second transistor, and

the first switch is in an off-state and the second switch is in an on-state in the boosting period.

3. The imaging device according to claim 2 , wherein a threshold voltage between the gate and the source of the first transistor is equal to a threshold voltage between the gate and the source of the second transistor.

4. The imaging device according to claim 2 , wherein the first switch is switched from an on-state to the off-state, and the second switch is switched from an off-state to the on-state immediately before the boosting period.

5. The imaging device according to claim 2 , wherein the selection transistor is switched from an on-state to an off-state, the first switch is switched from an on-state to the off-state, and the second switch is switched from an off-state to the on-state in an auto-zero period of the comparator before the boosting period.

6. The imaging device according to claim 5 , wherein the first switch is an N-channel MOSFET.

7. The imaging device according to claim 1 , wherein the photoelectric conversion element, the signal converter, and the selection transistor are arranged on a first semiconductor substrate, and the comparator and the correction circuit are arranged on a second semiconductor substrate stacked on the first semiconductor substrate.

8. The imaging device according to claim 1 , wherein the photoelectric conversion element, the signal converter, the selection transistor, the comparator, and the correction circuit are arranged on one semiconductor substrate.

9. The imaging device according to claim 1 , wherein

a plurality of the photoelectric conversion elements including the photoelectric conversion element is two-dimensionally arranged, and

the comparator and the correction circuit are provided for each of the plurality of photoelectric conversion elements.

10. The imaging device according to claim 9 adopting a global shutter system in which the plurality of photoelectric conversion elements accumulates the charge at a same timing.

11. The imaging device according to claim 9 adopting a rolling shutter system in which the plurality of photoelectric conversion elements accumulates the charge at different timings.

12. A distance measurement system, comprising:

an illumination device that emits distance measurement light; and

an imaging device that receives reflected light of the distance measurement light,

wherein the imaging device includes:

a photoelectric conversion element that photoelectrically converts the reflected light;

a signal converter that is boosted when charge transferred from the photoelectric conversion element is converted into a pixel signal;

a selection transistor that interrupts a signal line of the pixel signal during a boosting period of the signal converter;

a comparator including a non-inverting input terminal to which the pixel signal is input via the selection transistor, an inverting input terminal to which a ramp signal is input, and an output terminal which outputs a comparison result between the pixel signal and the ramp signal; and

a correction circuit that holds a potential of the non-inverting input terminal in the boosting period at a potential of the non-inverting input terminal before the boosting period.

13. The distance measurement system according to claim 12 , wherein

the correction circuit includes:

a first transistor arranged between the selection transistor and the non-inverting input terminal;

a second transistor paired with the first transistor;

a first switch arranged between a gate of the first transistor and a gate of the second transistor;

a second switch arranged between a source of the first transistor and a source of the second transistor; and

a capacitor connected to the gate of the second transistor, wherein the first switch is in an off-state and the second switch is in an on-state in the boosting period.

14. The distance measurement system according to claim 13 , wherein a threshold voltage between the gate and the source of the first transistor is equal to a threshold voltage between the gate and the source of the second transistor.

15. The distance measurement system according to claim 13 , wherein the first switch is switched from an on-state to the off-state, and the second switch is switched from an off-state to the on-state immediately before the boosting period.

16. The distance measurement system according to claim 12 , wherein the photoelectric conversion element, the signal converter, and the selection transistor are arranged on a first semiconductor substrate, and the comparator and the correction circuit are arranged on a second semiconductor substrate stacked on the first semiconductor substrate.

17. The distance measurement system according to claim 12 , wherein the photoelectric conversion element, the signal converter, the selection transistor, the comparator, and the correction circuit are arranged on one semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2023
From: KUMATA, KEISHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 064059/0175 →
Priority Claims (1)
JP 2021-000561 · Jan 5, 2021 · national
Continuity (1)
Related Publication 20240314467A1 · Sep 19, 2024
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